LTC1968 datasheet(3/28 Pages) LINER

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LTC1968

1968f

The

● denotes specifications which apply over the full operating

temperature range, otherwise specifications are TA = 25°C. V+ = 5V, VOUTRTN = 2.5V, CAVE = 10µF, VIN = 200mVRMS, VENABLE = 0.5V

unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: The inputs (IN1, IN2) are protected by shunt diodes to GND and

V+. If the inputs are driven beyond the rails, the current should be limited

to less than 10mA.

Note 3: The LTC1968 output (VOUT) is high impedance and can be

overdriven, either sinking or sourcing current, to the limits stated.

Note 4: The LTC1968C/LTC1968I are guaranteed functional over the

operating temperature range of – 40°C to 85°C.

Note 5: The LTC1968C is guaranteed to meet specified performance from

0°C to 70°C. The LTC1968C is designed, characterized and expected to

meet specified performance from – 40°C to 85°C but is not tested nor QA

sampled at these temperatures. The LTC1968I is guaranteed to meet

specified performance from – 40°C to 85°C.

Note 6: High speed automatic testing cannot be performed with

CAVE = 10µF. The LTC1968 is 100% tested with CAVE = 47nF.

Note 7: The LTC1968 is 100% tested with DC and 10kHz input signals.

Measurements with DC inputs from 50mV to 350mV are used to calculate

the four parameters: GERR, VOOS, VIOS and linearity error. Correlation tests

have shown that the performance limits can be guaranteed with the

additional testing being performed to guarantee proper operation of all

internal circuitry.

Note 8: The LTC1968 is inherently very linear. Unlike older log/antilog

circuits, its behavior is the same with DC and AC inputs, and DC inputs are

used for high speed testing.

Note 9: The power supply rejections of the LTC1968 are measured with

DC inputs from 50mV to 350mV. The change in accuracy from V+ = 4.5V

to V+ = 5.5V is divided by 1V.

Note 10: Previous generation RMS-to-DC converters required nonlinear

input stages as well as a nonlinear core. Some parts specify a “DC reversal

error,” combining the effects of input nonlinearity and input offset voltage.

The LTC1968 behavior is simpler to characterize and the input offset

voltage is the only significant source of “DC reversal error.”

Note 11: Guaranteed by design.

Note 12: The LTC1968 is a switched capacitor device and the input/output

impedance is an average impedance over many clock cycles. The input

impedance will not necessarily lead to an attenuation of the input signal

measured. Refer to the Applications Information section titled “Input

Impedance” for more information.

Note 13: The common mode rejection ratios of the LTC1968 are measured

with DC inputs from 50mV to 350mV. The input CMRR is defined as the

change in VIOS measured with the input common mode voltage at 0V and

V+, divided by V+. The output CMRR is defined as the change in VOOS

measured with OUT RTN = 0V and OUT RTN = V+ – 350mV divided by

V+ – 350mV.

Note 14: The LTC1968 input and output voltage swings are limited by

internal clipping. However, its ∆Σ topology is relatively tolerant of

momentary internal clipping.

Note 15: The LTC1968 exploits oversampling and noise shaping to reduce

the quantization noise of internal 1-bit analog-to-digital conversions. At

higher input frequencies, increasingly large portions of this noise are

aliased down to DC. Because the noise is shifted in frequency, it becomes

a low frequency rumble and is only filtered at the expense of increasingly

long settling times. The LTC1968 is inherently wideband, but the output

accuracy is degraded by this aliased noise.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Output Characteristics

OVR

Output Voltage Range

●

0V+

ZOUT

Output Impedance

(Note 12)

●

12.5

kΩ

CMRRO

Output Common Mode Rejection

(Note 13)

●

250

µV/V

VOMAX

Maximum Differential Output Swing

Accuracy = 1%, DC Input (Note 14)

1.0

1.05

●

0.9

PSRRO

Power Supply Rejection

(Note 9)

●

250

1000

µV/V

Frequency Response

f1P

1% Additional Gain Error (Note 15)

500

kHz

f–3dB

±3dB Frequency (Note 15)

MHz

Power Supplies

V+

Supply Voltage

●

4.5

5.5

Supply Current

IN1 = 20mV, IN2 = 0V

●

2.3

2.7

IN1 = 200mV, IN2 = 0V

2.4

Shutdown Characteristics

ISS

Supply Current

VENABLE = 4.5V

●

0.1

µA

IIH

ENABLE Pin Current High

VENABLE = 4.5V

●

–1

–0.1

µA

IIL

ENABLE Pin Current Low

VENABLE = 0.5V

●

–3

–0.5

– 0.1

µA

VTH

ENABLE Threshold Voltage

2.1

VHYS

ENABLE Threshold Hysteresis

0.1

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