13

LTC1968

1968f

Output Connections

The LTC1968 output is differentially, but not symmetri-

cally, generated. That is to say, the RMS value that the

LTC1968 computes will be generated on the output (Pin 5)

relative to the output return (Pin 6), but these two pins are

not interchangeable. For most applications, Pin 6 will be

tied to ground (Pin 1). However, Pin 6 can be tied to any

output voltage swing desired. This last restriction keeps

reference level other than ground is used, it should be a

low impedance, both AC and DC, for proper operation of

the LTC1968.

In any configuration, the averaging capacitor should be

connected between Pins 5 and 6. The LTC1968 RMS-DC

with respect to OUT RTN (Pin 6).

Power Supply Bypassing

The LTC1968 is a switched capacitor device, and large

transient power supply currents will be drawn as the

switching occurs. For reliable operation, standard power

supply bypassing must be included. A 0.01µF capacitor

will suffice. If there is a good quality ground plane avail-

able, the capacitors can go directly to that instead. Power

supply bypass capacitors can, of course, be inexpensive

ceramic types.

Up and Running!

If you have followed along this far, you should have the

LTC1968 up and running by now! Don’t forget to enable

the device by grounding Pin 8, or driving it with a logic low.

Keep in mind that the LTC1968 output impedance is fairly

high, and that even the standard 10MΩ input impedance

of a digital multimeter (DMM) or a 10× scopeprobewillload

down the output enough to degrade its typical gain error

of 0.1%. In the end application circuit, either a buffer or

another component with an extremely high input imped-

ance (such as a dual slope integrating ADC) should be used.

APPLICATIO S I FOR ATIO

For laboratory evaluation, it may suffice to use a bench-top

DMM with the ability to disconnect the 10MΩ shunt.

If you are still having trouble, it may be helpful to skip

ahead a few pages and review the Troubleshooting Guide.

What About Response Time?

With a large value averaging capacitor, the LTC1968 can

easily perform RMS-to-DC conversion on low frequency

signals. It compares quite favorably in this regard to prior-

generation products because nothing about the ∆Σ

circuitry is temperature sensitive. So the RMS result

doesn’t get distorted by signal driven thermal fluctuations

like a log-antilog circuit output does.

However, using large value capacitors results in a slow

response time. Figure 10 shows the rising and falling step

responses with a 10µF averaging capacitor. Although they

both appear at first glance to be standard exponential-

decay type settling, they are not. This is due to the

nonlinear nature of an RMS-to-DC calculation. Also note

the change in the time scale between the two; the rising

edge is more than twice as fast to settle to a given

accuracy. Again this is a necessary consequence of RMS-

Although shown with a step change between 0mV and

100mV, the same response shapes will occur with the

LTC1968 for ANY step size. This is in marked contrast to

prior generation log/antilog RMS-to-DC converters, whose

averaging time constants are dependent on the signal

level, resulting in excruciatingly long waits for the output

to go to zero.

The shape of the rising and falling edges will be dependent

on the total percent change in the step, but for less than the

100% changes shown in Figure 10, the responses will be

less distorted and more like a standard exponential decay.

For example, when the input amplitude is changed from

100mV. At very low frequencies, the LTC1968 will essentially track the input. But as the input

frequency is increased, the average result will converge to the RMS value of the input. If the rise and

fall characteristics were symmetrical, the output would converge to 50mV. In fact though, the RMS

value of a 100mV DC-coupled 50% duty cycle pulse train is 70.71mV, which the asymmetrical rise

and fall characteristics will converge to as the input frequency is increased.