M25P128

Operating features

Rev. 1

11/41

4.5

Status Register

The Status Register contains a number of status and control bits that can be read or set (as

appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a

detailed description of the Status Register bits.

4.6

Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can operate correctly in the presence of excessive noise. To help combat this, the

M25P128 features the following data protection mechanisms:

●

changes while the power supply is outside the operating specification.

●

Program, Erase and Write Status Register instructions are checked that they consist of

a number of clock pulses that is a multiple of eight, before they are accepted for

execution.

●

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state

by the following events:

–Power-up

–

Write Disable (WRDI) instruction completion

–

Write Status Register (WRSR) instruction completion

–

Page Program (PP) instruction completion

–

Sector Erase (SE) instruction completion

–

Bulk Erase (BE) instruction completion

●

The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as

read-only. This is the Software Protected Mode (SPM).

●

The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status

Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected

Mode (HPM).

Table 2.

Protected Area Sizes

Status Register Content

Memory Content

BP2 Bit BP1 Bit BP0 Bit

Protected Area

Unprotected Area

0

0

0

none

1.

The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.

0

0

1

Upper 64th (1 Sector, 2Mb)

Sectors 0 to 62

0

1

0

Upper 32nd (2 Sectors, 4Mb)

Sectors 0 to 61

0

1

1

Upper 16nd (4 Sectors, 8Mb)

Sectors 0 to 59

1

0

0

Upper 8nd (8 Sectors, 16Mb)

Sectors 0 to 55

1

0

1

Upper Quarter (16 Sectors, 32Mb) Lower 3 Quarters (Sectors 0 to 47)

1

1

0

Upper Half (32 Sectors, 64Mb)

Lower Half (Sectors 0 to 31)

1

1

1

All sectors (64 Sectors, 128Mb)

none