EDSTRG28PLCCCX datasheet(39/78 Pages) TI

39 / 78 page

GLOSSARY/SYMBOLS, TERMS, AND DEFINITIONS

1–31

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CSPF:

Chip-Select Peripheral File. This signal has the same timing as EDS, but it goes active only during access

to external frames of the peripheral field (locations 10C0h – 10FFh).

data:

Any information stored in or retrieved from a memory device.

debugger:

A window-oriented software interface that helps the user to debug ’370 programs running on an

emulator, CDT370, or design kit.

dedicated-capture registers:

An area in the PACT module dual-port RAM that stores the value of the default timer

at the time of a specified edge on one of the PACT input-capture pins. Unlike the circular buffer, the location of

the dedicated-capture register does not change.

default timer (also hardware timer):

A 20-bit hardware counter in the PACT module that is incremented by the

PACT prescaled clock

design kit:

A low-cost tool that allows the user to analyze the hardware and software capabilities of the TMS370

family.

DIP:

Dual In-line Package

dual-port RAM:

An area in RAM that can be read from and written to by both the TMS370 CPU and the PACT

module.

edge detection:

A type of circuitry that senses an active pulse transition on a given timer input and provides ap-

propriate output transitions to the rest of the module. The active transition can be configured to be low-to-high or

high-to-low.

EDS:

External Data Strobe. This signal goes low during external-memory operations. The rising edge of EDS vali-

dates the read-input data; the write data is available after the falling edge of EDS.

EEPROM:

Electrically Erasable Programmable Read-Only Memory. Memory that can be programmed and erased

under direct program control.

EPROM:

Erasable Programmable Read-Only Memory. Memory that can be programmed under direct program

control.

Erase:

Typically associated with EPROM and EEPROM. The procedure whereby programmed data is removed

and the device returns to its unprogrammed state.

ESD:

Electrostatic discharge

fully-static RAM:

In a fully-static RAM, the periphery as well as the memory array is fully static. The periphery is

therefore always active and ready to respond to input changes without the need of clocks. There is no precharge

required for static periphery.

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