ACE25AA800GFMLTH datasheet(7/50 Pages) ACE

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ACE25AA800G

Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase

VER 1.1

Table 1.1ACE25AA800G Protected Area Sizes (CMP=1)

Status bit

Memory Content

BP3

BP2

BP1

BP0

Blocks

Addresses

Density

Portion

None

Block 0

000000H – 010000H

64KB

Upper 1/16

Block 0 – 1

000000H – 020000H

128K

Upper 1/8

Block 0 – 3

000000H – 040000H

256K

Upper 1/4

Block 0 – 7

000000H – 080000H

512K

Upper 1/2

Protected all

000000H – 100000H

All

Protected all

000000H – 100000H

All

Protected all

000000H – 100000H

All

Protected all

000000H – 100000H

All

Status Register

S15

S14

S13

S12

S11

S10

SUS

CMP

Reserved

SRP

Reserved

BP3

BP2

BP1

BP0

WEL

WIP

The status and control bits of the Status Register are as follows:

WIP bit.

The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status

progress, When WIP bit sets 0, means the device is not in program/ erase/ write status register progress.

WEL bit.

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1

the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no Write

Status Register, Program or Erase command is accepted.

BP3,BP2, BP1,BP0 bits.

The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be

software protected against Program and Erase commands. These bits are written with the Write Status

memory area (as defined in Table1) becomes protected against Page Program (PP), Sector Erase (SE)

and Block Erase (BE) commands. The Block Protect (BP3, BP2, BP1, BP0) bits can be written provided

that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed, if the

Block Protect (BP3, BP2, BP1, BP0) bits are all 0.

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