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ACE25AA800GFMLTH датащи(PDF) 26 Page - ACE Technology Co., LTD.

номер детали ACE25AA800GFMLTH
подробное описание детали  Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
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производитель  ACE [ACE Technology Co., LTD.]
домашняя страница  http://www.ace-ele.com
Logo ACE - ACE Technology Co., LTD.

ACE25AA800GFMLTH датащи(HTML) 26 Page - ACE Technology Co., LTD.

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ACE25AA800G
Serial NOR Flash Memory 3.0V Multi I/O with 4KB,32KB & 64KB Sector/Block Erase
VER 1.1
26
Deep Power-Down (DP) (B9H)
Executing the Deep Power-Down (DP) command is the only way to put the device in the lowest
consumption mode (the Deep Power-Down Mode). It can also be used as an extra software protection
mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program
and Erase commands. Driving CS# high deselects the device, and puts the device in the Standby Mode (if
there is no internal cycle currently in progress). But this mode is not the Deep Power-Down Mode. The
Deep Power-Down Mode can only be entered by executing the Deep Power-Down (DP) command. Once
the device has entered the Deep Power- Down Mode, all commands are ignored except the Release from
Deep Power-Down and Read Device ID (RDI) command. This releases the device from this mode. The
Release from Deep Power-Down and Read Device ID (RDI) command also allows the Device ID of the
device to be output on SO.
The Deep Power-Down Mode automatically stops at Power-Down, and the device always Power-Up in
the Standby Mode. The Deep Power-Down (DP) command is entered by driving CS# low, followed by the
command code on SI. CS# must be driven low for the entire duration of the sequence.
The Deep Power-Down command sequence: CS# goes low, sending Deep Power-Down command, CS#
goes high. The command sequence is shown in Figure 23. CS# must be driven high after the eighth bit of
the command code has been latched in; otherwise the Deep Power-Down (DP) command is not executed.
As soon as CS# is driven high, it requires a delay of tDP before the supply current is reduced to ICC2 and
the Deep Power- Down Mode is entered. Any Deep Power-Down (DP) command, while an Erase,
Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure22. Chip Erase Sequence Diagram
Figure23. Deep Power-Down Sequence Diagram



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