ADF4372 datasheet(21/47 Pages) AD

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Data Sheet

ADF4372

Rev. 0 | Page 21 of 47

DOUBLER

The VCO frequency multiplied by 2 is available at the RF16P

pin and RF16N pin. This output can be powered down when

not in use, and the RF16P pin and the RF16N pin can be left open

if unused.

RF16P

×2

RF16N

Figure 36. Doubler Output Stage

An automatic tracking filter on the ADF4372 that suppresses

the VCO and other unwanted frequency products ensures the

doubled output is maximized and that the VCO and 3 × VCO

frequencies are suppressed regardless of the output frequency.

Suppression of <50 dB is typical. The optimum values are set

automatically by the automatic tracking when it is enabled

using Bit 1 in Address 0x23.

The settings for optimum output power, phase noise, and

harmonic rejection are given in Table 6.

Table 6. Filter and Bias Settings for Doubled Output

Frequency (GHz)

Filter

Bias

<8.4

8.4 to 9.4

9.4 to 10

10 to 11.5

11.5 to 12.2

12.2 to 13.7

13.7 to 14.5

>14.5

OUTPUT STAGE MUTE

Another feature of the ADF4372 is that the supply current

to the RF8P and RF8N output stage can shut down until the

ADF4372 achieves lock as measured by the digital lock detect

circuitry. The mute to lock detect bit (MUTE_LD) in Address 0x25

enables this function.

SPI

The SPI of the ADF4372 allows the user to configure the device

as required via a 3-wire or 4-wire SPI port. This interface provides

users with added flexibility and customization. The serial port

interface consists of four control lines: SCLK, SDIO, CS, and

MUXOUT (not used in 3-wire SPI). The timing requirements

for the SPI port are detailed in Table 2.

The SPI protocol consists of a read and write bit and 15 register

address bits, followed by eight data bits. Both the address and data

fields are organized with the MSB first and end with the LSB

by default. The timing diagrams for write mode and read mode

are shown in Figure 3 and Figure 4, respectively. The significant

bit order can be changed via the Bit 1 (LSB_FIRST) setting at

Address 0x00. The related timing diagram is shown in Figure 2.

The ADF4372 input logic level for the write cycle is compatible

with 1.8 V logic level (see the logic parameters in Table 1). On a

read cycle, both the SDIO pin and MUXOUT pin are configurable

for 1.8 V (default) or 3.3 V output levels by the LEV_SEL bit

setting.

SPI Stream Mode

The ADF4372 supports stream mode, where data bits are loaded

to or read from registers serially without writing the register

address (instruction word). This mode is useful in time critical

applications, when a large amount of data must be transferred or

when some registers must be updated repeatedly.

The slave device starts reading or writing data to this address and

continues as long as CS is asserted and single-byte writes are not

enabled (Bit 7 in Address 0x01). The slave device automatically

increments or decrements the address depending on the setting

of the address ascension bit (Bit 2 in Address 0x00).

The diagram of 3-byte streaming is shown in Figure 5. The

instruction header starts with a Logic 0 to indicate a write

sequence and addresses the register. The data for registers (N,

N − 1, and N − 2) are loaded consecutively without any assertion

in CS.

The registers are organized into eight bits, and if a register

requires more than eight bits, sequential register addresses

are used. This organization enables using stream mode and

simplifies loading. For example, FRAC1WORD is stored in

Address 0x16, Address 0x15, and Address 0x14 (MSB to LSB).

These registers can be loaded by using Address 0x16 and sending

the whole 24-bit data afterward, as shown in Figure 5.

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