ADF4372 datasheet(39/47 Pages) AD

39 / 47 page

Data Sheet

ADF4372

Rev. 0 | Page 39 of 47

Address: 0x2F, Default: 0x94, Name: REG002F

Switch LDO Operation Between 3.3

V and 5 V.

Select VCO ALC Thres hold (Core

A).

Select ALC Lower Thres hold Voltage

Range (Core A).

Sets ALC Rectifier DC Bias (Core

A).

[7] SWITCH_LDO_3P3V_5V (R/W)

[2:0] ALC_REF_DAC_NOM_VCO4 (R/W)

[6:5] RESERVED

[3] ALC_REF_DAC_LO_VCO4 (R/W)

[4] ALC_RECT_SELECT_VCO4 (R/W)

Table 43. Bit Descriptions for REG002F

Bit(s)

Bit Name

Description

Default

Access

SWITCH_LDO_3P3V_5V

Switch LDO Operation Between 3.3 V and 5 V.

0x1

R/W

0: 3.3 V VCO operation.

1: 5 V VCO operation.

[6:5]

RESERVED

Reserved.

0x0

ALC_RECT_SELECT_VCO4

Sets ALC Rectifier DC Bias (Core A).

0x1

R/W

0: 3.3 V VCO operation.

1: 5 V VCO operation.

ALC_REF_DAC_LO_VCO4

Select ALC Lower Threshold Voltage Range (Core A).

0x0

R/W

0: 5 V VCO operation.

1: 3.3 V VCO operation.

[2:0]

ALC_REF_DAC_NOM_VCO4

Select VCO ALC Threshold (Core A).

0x4

R/W

010: 3.3 V VCO operation.

100: 5 V VCO operation.

Address: 0x30, Default: 0x3F, Name: REG0030

Sets the Autocalibration Tim e per

Stage.

[7:0] VCO_BAND_DIV (R/W)

Table 44. Bit Descriptions for REG0030

Bit(s)

Bit Name

Description

Default

Access

[7:0]

VCO_BAND_DIV

Sets the Autocalibration Time per Stage. See the Lock Time section for details.

0x3F

R/W

Address: 0x31, Default: 0xA7, Name: REG0031

Us ed as Part of the ALC Wait Tim e

and Synthetic Lock Tim e.

[7:0] TIMEOUT[7:0] (R/W)

Table 45. Bit Descriptions for REG0031

Bit(s)

Bit Name

Description

Default

Access

[7:0]

TIMEOUT[7:0]

Used as Part of the ALC Wait Time and Synthetic Lock Time. See the Lock Time section for details.

0xA7

R/W

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