DS90C241/DS90C124

5-35MHz DC-Balanced 24-Bit LVDS Serializer and

Deserializer

General Description

The DS90C241/124 Chipset translates a 24-bit parallel bus

into a fully transparent data/control LVDS serial stream with

embedded clock information. This single serial stream sim-

plifies transferring a 24-bit bus over PCB traces and cable by

eliminating the skew problems between parallel data and

clock paths. It saves system cost by narrowing data paths

that in turn reduce PCB layers, cable width, and connector

size and pins.

The DS90C241/124 incorporates LVDS signaling on the

high-speed I/O. LVDS provides a low power and low noise

environment for reliably transferring data over a serial trans-

mission path. By optimizing the serializer output edge rate

for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals

over longer distances using lossy cables. Internal DC bal-

anced encoding/decoding is used to support AC-Coupled

interconnects.

Features

n

5 MHz–35 MHz clock embedded and DC-Balancing

1:24 and 24:1 data transmissions

n

User defined pre-emphasis driving ability through

external resistor on LVDS outputs and capable to drive

up to 10 meters shielded twisted-pair cable

n

User selectable clock edge for parallel data on both TX

and RX

n

Supports AC-coupling interface

n

Individual power-down controls for both TX and RX

n

Embedded clock CDR (clock and data recovery) on RX

and no external source of reference clock needed

n

All codes RDL (random data lock) to support

hot-pluggable applications

n

LOCK output flag to ensure data integrity at RX side

n

Balanced T

RX side

n

PTO (progressive turn-on) LVTTL O/P to minimize the

SSO effects

n

All LVTTL inputs and control pins have internal pulldown

except PRE

n

On-chip filters for PLLs on TX and RX

n

48 pin TQFP package for both TX and RX

n

Pure CMOS .35 µm process

n

n

Temperature range –40˚C to +105˚C

n

8 kV HBM ESD structure

Block Diagram

20171901

PRELIMINARY

January 2006

© 2006 National Semiconductor Corporation

DS201719

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