WM8774IFT datasheet(24/42 Pages) WOLFSON

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WM8774

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PP Rev 1.0 June 2002

DAC ANALOGUE VOLUME CONTROL

The DAC volume may be adjusted independently in both the analogue and digital domain using

separate volume control registers.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

6:0

LA[6:0]

1111111

(0dB)

Attenuation data for Left channel DACL in 1dB steps. See Table 10

LZCEN

DACL zero cross detect enable

0: zero cross disabled

1: zero cross enabled

00000

Analogue

Attenuation

DACL

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store LA in intermediate latch (no change to output)

1: Store LA and update attenuation on all channels.

6:0

RA[6:0]

1111111

(0dB)

Attenuation data for Right channel DACR in 1dB steps. See Table 10

RZCEN

DACR zero cross detect enable

0: zero cross disabled

1: zero cross enabled

00001

Analogue

Attenuation

DACR

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store RA in intermediate latch (no change to output)

1: Store RA and update attenuation on all channels.

6:0

MASTA[6:0]

1111111

(0dB)

Attenuation data for all channel DAC in 1dB steps. See Table 10

MZCEN

Master zero cross detect enable

0: zero cross disabled

1: zero cross enabled

01000

Master

Analogue

Attenuation

(both channels)

UPDATE

Not latched

Controls simultaneous update of all Attenuation Latches

0: Store gain in intermediate latch (no change to output)

1: Store gain and update attenuation on all channels.

Table 9 Attenuation Register Map

Each DAC channel volume can be controlled digitally in an analogue volume stage after the DAC.

Attenuation is 0dB by default but can be set between 0 and –100dB in 1dB steps using the 7

Attenuation control words. All attenuation registers are double latched allowing new values to be pre-

latched to several channels before being updated synchronously. Setting the UPDATE bit on any

attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. A

master attenuation register is also included, allowing all volume levels to be set to the same value in

a single write.

Note: The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the pre-

latch but not applied to the relevant DAC. If UPDATE=1, all pre-latched values will be applied from

the next input sample. Writing to MASTA[6:0] overwrites any values previously sent to LA[6:0] and

RA[6:0].

In addition a zero cross detect circuit is provided for each DAC volume under the control of bit 7

(xZCEN) in each DAC attenuation register. When ZCEN is set the attenuation values are only

updated when the input signal to the gain stage is close to the analogue ground level. This minimises

audible clicks and ‘zipper’ noise as the gain values change. A timeout clock is also provided which

will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of

12.288MHz). The timeout clock may be disabled by setting TOD.

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