ADPD105BCPZ datasheet(62/66 Pages) AD

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ADPD105/ADPD106/ADPD107

Data Sheet

Rev. A | Page 62 of 66

Address

Data

Bit

Default

Access

Name

Description

0x38

[15:0]

0x0000

R/W

EXT_SYNC_STARTUP

Write 0x4000 when EXT_SYNC_SEL is b01 or b10. Otherwise, write 0x0.

0x4B

[15:9]

0x13

R/W

Reserved

Write 0x26.

0x0

R/W

CLK32K_BYP

Bypass internal 32 kHz oscillator.

0x0: normal operation.

0x1: provide external clock on the GPIO1 pin. The user must set

0x0

R/W

CLK32K_EN

Sample clock power-up. Enables the data sample clock.

0x0: clock disabled.

0x1: normal operation.

0x0

R/W

Reserved

Write 0x0.

[5:0]

0x12

R/W

CLK32K_ADJUST

Data sampling (32 kHz) clock frequency adjust. This register is used to

calibrate the sample frequency of the device to achieve high precision

on the data rate as defined in Register 0x12. Adjusts the sample master

32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in

Note that a larger value produces a lower frequency. See the Clocks

and Timing Calibration section for more information regarding clock

adjustment.

00 0000: maximum frequency.

10 0010: typical center frequency.

11 1111: minimum frequency.

0x4D

[15:8]

0x00

R/W

Reserved

Write 0x00.

[7:0]

0x98

R/W

CLK32M_ADJUST

Internal timing (32 MHz) clock frequency adjust. This register is used to

calibrate the internal clock of the device to achieve precisely timed LED

pulses. Adjusts the 32 MHz clock by 109 kHz per LSB.

See the Clocks and Timing Calibration section for more information

regarding clock adjustment.

0000 0000: minimum frequency.

1001 1000: default frequency.

1111 1111: maximum frequency.

0x4E1

[15:0]

0x0060

R/W

ADC_TIMING1

0x0040: ADC clock speed = 1 MHz.

0x0060: ADC clock speed = 500 kHz.

0x4F

[15:8]

0x20

R/W

Reserved

Write 0x20.

0x1

R/W

Reserved

Write 0x1.

0x0

R/W

GPIO1_OE

GPIO1 pin output enable.

0x0

R/W

GPIO1_IE

GPIO1 pin input enable.

0x1

R/W

Reserved

Write 0x1.

[3:2]

0x0

R/W

EXT_SYNC_SEL

Sample sync select.

00: use the internal 32 kHz clock with FSAMPLE to select sample timings.

01: use the GPIO0 pin to trigger sample cycle.

10: use the GPIO1 pin to trigger sample cycle.

11: reserved.

0x0

R/W

GPIO0_IE

GPIO0 pin input enable.

0x0

R/W

Reserved

Write 0x0.

0x50

[15:7]

0x000

R/W

Reserved

Write 0x000.

0x0

R/W

GPIO1_CTRL

Controls the GPIO1 output when the GPIO1 output is enabled

(GPIO1_OE = 0x1).

0x0: GPIO1 output driven low.

0x1: GPIO1 output driven by the AFE power-down signal.

0x0

R/W

CLK32M_CAL_EN

As part of the 32 MHz clock calibration routine, write 1 to begin the

clock ratio calculation. Read the result of this calculation from the

CLK_RATIO bits in Register 0x0A.

Reset this bit to 0 prior to reinitiating the calculation.

[4:0]

0x00

R/W

Reserved

Write 0x0.

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