ADPD105BCPZ datasheet(40/66 Pages) AD

40 / 66 page

ADPD105/ADPD106/ADPD107

Data Sheet

Rev. A | Page 40 of 66

Powering Down Individual Amplifiers for Additional

Power Savings

Each channel includes a TIA, a BPF, and an integrator, which

can also be configured as a buffer (see Figure 44).Options are

built into the devices to power down individual amplifiers in the

signal path. For example, in digital integrate mode, the BPF is

bypassed but left powered up by default. The BPF can be disabled

completely, which saves 1/3 of the power dissipated by the AFE

during the sampling phase. See the descriptions for Register 0x3C

and Register 0x37 in Table 30 for information on how to disable

the individual amplifiers.

TIA

VBIAS

BPF

±1 INTEGRATOR

Figure 44. Signal Path Block Diagram

It is important to leave any unused input channels floating for

proper device operation.

TIA ADC MODE

There is a way to put the devices into a mode that effectively runs

the TIA directly into the ADC without using the analog band-pass

filter and integrator as shown in Figure 45. This mode is referred to

as TIA ADC mode. There are two basic applications of TIA ADC

mode. In normal operation, all of the background light is blocked

from the signal chain, and therefore cannot be measured. TIA_

ADC mode can be used to measure the amount of background/

ambient light. This mode can also be used to measure other dc

input currents, such as leakage resistance.

VBIAS

OPTIONAL

BUFFER

–1

TIA

ADC

Figure 45. TIA ADC Mode Block Diagram

When the devices are in TIA ADC mode, the band-pass filter

and the integrator stage are bypassed. This bypass effectively

wires the TIA directly into the ADC. At the set sampling

frequency, the ADC samples Channel 1 through Channel 4 in

sequential order, and each sample is taken at 1 μs intervals.

There are two modes of operation in TIA ADC mode. One

mode is an inverting configuration where TIA ADC mode

directly drives the ADC. This mode is enabled by setting

to 0xB065, which bypasses the band-pass filter and the

integrator. With the ADC offset register(s) for the desired

channel set to 0, the output of the ADC is at ~13,000 codes for a

single pulse and a zero input current condition. As the input

current from the photodiode increases, the ADC output

decreases toward 0. This configuration is a legacy TIA ADC

mode from the ADPD103 that is kept in the ADPD105/

ADPD106/ADPD107 for backward compatibility.

The recommended TIA ADC mode is one in which the band-

pass filter is bypassed and the integrator is configured as an

inverting buffer. This mode is enabled by writing 0xAE65 to

to bypass the band-pass filter. Additionally, Bit 7 of Register 0x42

(Time Slot A) and/or Register 0x44 (Time Slot B) must be set to

1 to configure the integrator as a buffer. With the ADC offset

ADC is at ~3000 codes for a single pulse and a zero input

current condition. As the input current from the photodiode

increases, the ADC output increases toward 16,384.

The ADC output (ADCOUT) is calculated as follows:

ADCOUT = 8192 ± ((2 VBIAS − 2iRF − 1.8 V)/146 μV/LSB) (11)

where:

VBIAS is the bias voltage for the TIA (the default value is 1.265 V).

i is the input current to the TIA.

RF is the TIA feedback resistor.

In Equation 11, use + for the inverting configuration and use −

when using the noninverting configuration with the buffer.

Equation 11 is an approximation and does not account for

internal offsets and gain errors. The calculation also assumes

that the ADC offset registers are set to 0

One time slot can be used in TIA ADC mode at the same time

the other time slot is being used in normal pulsed mode. This

capability is useful for monitoring ambient and pulsed signals at

the same time. The ambient signal is monitored during the time

slot configured for TIA ADC mode, while the pulsed signal,

with the ambient signal rejected, is monitored in the time slot

configured for normal mode.

Protecting Against TIA Saturation in Normal Operation

One of the reasons to monitor TIA ADC mode is to protect

against environments that may cause saturation. One concern

when operating in high light conditions, especially with larger

photodiodes, is that the TIA stage may become saturated while

the ADPD105/ADPD106/ADPD107 continue to communicate

data. The resulting saturation is not typical. The TIA, based on its

settings, can only handle a certain level of photodiode current.

Based on the way the ADPD105/ADPD106/ADPD107 are

configured, if there is a current level from the photodiode that is

larger than the TIA can handle, the TIA output during the LED

pulse effectively extends the current pulse, making it wider. The

AFE timing is then violated because the positive portion of the

band-pass filter output extends into the negative section of the

integration window. Thus, the photosignal is subtracted from

itself, causing the output signal to decrease when the effective

light signal increases.

To measure the response from the TIA and verify that this stage

is not saturating, place the device in TIA ADC mode and slightly

modify the timing. Specifically, sweep SLOTx_AFE_OFFSET

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