MCP3302 datasheet(18/40 Pages) MICROCHIP

18 / 40 page

MCP3302/04

DS21697B-page 18

 2002 Microchip Technology Inc.

FIGURE 6-3:

Analog Input Model.

6.2.1

MAINTAINING MINIMUM CLOCK

SPEED

When the MCP3302/04 initiates, charge is stored on

the sample capacitor. When the sample period is com-

plete, the device converts one bit for each clock that is

received. It is important for the user to note that a slow

clock rate will allow charge to bleed off the sample cap

while the conversion is taking place. For the MCP330X

devices, the recommended minimum clock speed dur-

ing the conversion cycle (TCONV) is 105 kHz. Failure to

meet this criteria may induce linearity errors into the

conversion outside the rated specifications. It should

be noted that during the entire conversion cycle, the

A/D converter does not have requirements for clock

speed or duty cycle, as long as all timing specifications

are met.

6.3

Biasing Solutions

For pseudo-differential bipolar operation, the biasing

circuit (shown in Figure 6-4) shows a single ended

input AC coupled to the converter. This configuration

will give a digital output range of -4096 to +4095. With

the 2.5V reference, the LSB size equal to 610

µV.

Although the ADC is not production tested with a 2.5V

reference as shown, linearity will not change more than

0.1 LSB. See Figure 2-2 and Figure 2-9 for DNL and

INL errors versus VREF at VDD = 5V. A trade-off exists

between the high pass corner and the acquisition time.

The value of C will need to be quite large in order to

bring down the high pass corner. The value of R will

need to be 1 k

Ω, or less, since higher input impedances

require additional acquisition time. Using the RC values

in Figure 6-4, we have a 100 Hz corner frequency. See

Figure 2-12 for relation between input impedance and

acquisition time.

FIGURE 6-4:

Pseudo-differential biasing

circuit for bipolar operation.

Using an external operation amplifier on the input

allows for gain and also buffers the input signal from the

input to the ADC allowing for a higher source imped-

ance. This circuit is shown in Figure 6-5.

CPIN

RSS CHx

7pF

VT = 0.6V

ILEAKAGE

Sampling

Switch

RS = 1 kΩ

CSAMPLE

= DAC capacitance

VSS

VDD

= 25 pF

±1 nA

Legend

= signal source

RSS = source impedance

CHx

= input channel pad

CPIN = input pin capacitance

VT = threshold voltage

ILEAKAGE = leakage current at the pin

due to various junctions

= sampling switch

RS = sampling switch resistor

CSAMPLE = sample/hold capacitance

VDD = 5V

0.1 µF

IN+

IN-

VREF

MCP330X

1µF

MCP1525

VIN

VOUT

0.1 µF

Ω

10 µF

VIN

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