MCP3302 datasheet(17/40 Pages) MICROCHIP

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 2002 Microchip Technology Inc.

DS21697B-page 17

MCP3302/04

6.0

APPLICATIONS INFORMATION

6.1

Conversion Description

The MCP3302/04 A/D converters employ a conven-

tional SAR architecture. With this architecture, the

potential between the IN+ and IN- inputs are simulta-

neously sampled and stored with the internal sample

circuits for 1.5 clock cycles. Following this sampling

time, the input hold switches of the converter open and

the device uses the collected charge to produce a

serial 13-bit binary two’s complement output code. This

conversion process is driven by the external clock and

must include 13 clock cycles, one for each bit. During

this process, the most significant bit (MSB) is output

first. This bit is the sign bit and indicates if the IN+ or IN-

input is at a higher potential.

FIGURE 6-1:

Simplified Block Diagram.

6.2

Driving the Analog Input

The analog input of the MCP3302/04 is easily driven,

either differentially or single ended. Any signal that is

common to the two input channels will be rejected by

the common mode rejection of the device. During the

charging time of the sample capacitor, a small charging

current will be required. For low source impedances,

this input can be driven directly. For larger source

impedances, a larger acquisition time will be required

due to the RC time constant that includes the source

impedance. For the A/D Converter to meet specifica-

tion, the charge holding capacitor (CSAMPLE) must be

given enough time to acquire a 13-bit accurate voltage

level during the 1.5 clock cycle acquisition period.

An analog input model is shown in Figure 6-3. This

model is accurate for an analog input, regardless if it is

configured as a single ended input, or the IN+ and IN-

input in differential mode. In this diagram, it is shown

that the source impedance (RS) adds to the internal

sampling switch (RSS) impedance, directly affecting the

time that is required to charge the capacitor (CSAMPLE).

Consequently, a larger source impedance with no addi-

tional acquisition time increases the offset, gain and

integral linearity errors of the conversion. To overcome

this, a slower clock speed can be used to allow for the

longer charging time. Figure 6-2 shows the maximum

clock speed associated with source impedances.

FIGURE 6-2:

Maximum Clock Frequency

vs. Source Resistance (RS) to maintain ±1 LSB

INL.

Comp

13-Bit SAR

CDAC

IN+

IN-

Shift

CSAMP

Hold

CSAMP

DOUT

0.0

0.5

1.0

1.5

2.0

2.5

100

1000

10000

100000

Source Resistance (ohms)

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