TMP47P201 datasheet(17/32 Pages) TOSHIBA

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TMP47C101/201

Figure 2-21. Interrupt Controller Block Diagram

(1)

Interrupt enable master ﬂip-ﬂop (EIF)

The EIF controls the enable/disable of all interrupts.

When this ﬂip-ﬂop is cleared to “0”, all interrupts are

disabled; when it is set to “1”, the interrupts are

enabled.

When an interrupt is accepted, the EIF is cleared to

“0”, temporarily disabling the acceptance of subse-

quent interrupts.

When the interrupt service program has been exe-

cuted, the EIF is set to “1” by the execution of the

interrupt return instruction [RETI], being put in the

enabled state again.

Set or clear of the EIF in program is performed by

instruction [EICLR IL, r] and [DICLR IL, R], respectively.

The EIF is initialized to “0” during reset.

(2)

Interrupt enable register (EIR)

The EIR is a 4-bit register speciﬁes the enable or dis-

able of each interrupt except INT1. An interrupt is

enabled when the corresponding bit of the EIR is “1”,

and an interrupt is disabled when the corresponding

bit of the EIR is “0”. Bit 1 of the EIR (EIR1) is shared by

both IOVF2 and ITMR interrupts.

Read/write on the EIR is performed by executing [SCH

a, EIR] instruction. The EIR initialized to “0” during

reset.

(3)

Interrupt latch (IL5 through IL0)

An interrupt latch is provided for each interrupt source.

The IL is set to “1” when an interrupt request is made

to ask the CPU for accepting the interrupt. Each IL is

cleared to “0” upon acceptance of the interrupt. It is

initialized to “0” during reset.

The ILS can be cleared independently by interrupt

latch operation instructions ([EICLR IL, r], [DICLR IL, r],

and [CLR IL, r]) to make them cancel interrupt requests

or initialize by program. When the value of instruction

ﬁeld (r) is “0”, the interrupt latch is cleared; when the

value is “1”, the IL is held. Note that the ILs cannot be

set by instruction.

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