receiving any data byte, or generating a start or stop condition. If repeated reads from the same register are

desired, it is not necessary to continually send the register pointer bytes; the device retains the register pointer

value until it is changed by the next write operation.

Figure 7-7 shows the write operation timing diagram. Figure 7-8 shows the read operation timing diagram. These

diagrams are shown for reading/writing to 16 bit registers. Registers with a higher number of bytes will behave

similarly.

Register bytes are sent most-significant byte first, followed by the least significant byte.

Frame 1 Two-Wire Secondary Address Byte

(1)

Frame 2 Register Pointer Byte

Start By

Main

ACK By

Secondary

ACK By

Secondary

1

9

1

ACK By

Secondary

1

D15 D14

D13

D12 D11 D10

D9

D8

9

9

SDA

SCL

1

0

0

A3

A2

A1

A0

P7

P6

P5

P4

P3

P2

P1

P0

Frame 4 Data LSByte

Frame 3 Data MSByte

ACK By

Secondary

Stop By

Main

1

D7

D6

D5

D4

D3

D2

D1

D0

9

A. The value of the Secondary Device Address byte is determined by the settings of the A0 and A1 pins. Refer to Table 7-2.

B. The device does not support packet error checking (PEC) or perform clock stretching.

Figure 7-7. Timing Diagram for Write Word Format

Frame 1 Two-Wire Secondary Address Byte

(1)

Frame 2 Data MSByte

(2)

1

Start By

Main

ACK By

Secondary

ACK By

Main

From

Secondary

1

9

1

9

SDA

SCL

0

0

A3

D15 D14 D13

D12

D11 D10

D9

D8

A2

A1

A0

Frame 3 Data LSByte

(2)

Stop

No ACK By

(3)

Main

From

Secondary

1

9

D7

D6

D5

D4

D3

D2

D1

D0

A. The value of the Secondary Device Address byte is determined by the settings of the A0 and A1 pins. Refer to Table 7-2.

B. Read data is from the last register pointer location. If a new register is desired, the register pointer must be updated. See Figure 7-9.

C. ACK by the main device can also be sent.

D. The device does not support packet error checking (PEC) or perform clock stretching.

Figure 7-8. Timing Diagram for Read Word Format

Frame 1 Two-Wire Secondary Address Byte

(1)

Frame 2 Register Pointer Byte

1

Start By

Main

ACK By

Secondary

ACK By

Secondary

1

9

1

9

SDA

SCL

0

0

A3

A2

A1

A0

P7

P6

P5

P4

P3

P2

P1

P0

Stop

¢

A. The value of the Secondary Device Address Byte is determined by the settings of the A0 and A1 pins. Refer to Table 7-2.

Figure 7-9. Typical Register Pointer Set

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The main device

generates a start condition followed by a valid serial byte containing high-speed (HS) main device code

00001XXX. This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400

kHz. The device does not acknowledge the HS main device code, but does recognize it and switches its internal

filters to support 2.94-MHz operation.

The main device then generates a repeated start condition (a repeated start condition has the same timing as

the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that

transmission speeds up to 2.94 MHz are allowed. Instead of using a stop condition, use repeated start

INA228

SLYS021 – JANUARY 2021

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