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INA228 датащи(PDF) 14 Page - Texas Instruments

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номер детали INA228
подробное описание детали  INA228 85-V, 20-Bit, Ultra-Precise Power/Energy/Charge Monitor With I2C Interface
PDF  48 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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INA228 датащи(HTML) 14 Page - Texas Instruments

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shunt voltage or bus voltage to further allow the user to configure the monitoring function to fit the specific
application requirements. When no averaging is selected, once an ADC conversion is completed, the converted
values are independently updated in their corresponding registers where they can be read through the digital
interface at the time of conversion end. The conversion time for shunt voltage, bus voltage, and temperature
inputs are set independently from 50 µs to 4.12ms depending on the values programmed in the ADC_CONFIG
register. Enabled measurement inputs are converted sequentially so the total time to convert all inputs depends
on the conversion time for each input and the number of inputs enabled. When averaging is used, the
intermediate values are subsequently stored in an averaging accumulator, and the conversion sequence repeats
until the number of averages is reached. After all of the averaging has been completed, the final values are
updated in the corresponding registers that can then be read. These values remain in the data output registers
until they are replaced by the next fully completed conversion results. In this case, reading the data output
registers does not affect a conversion in progress.
The ADC has two conversion modes—continuous and triggered—set by the MODE bits in ADC_CONFIG
register. In continuous-conversion mode, the ADC will continuously convert the input measurements and update
the output registers as described above in an indefinite loop. In triggered-conversion mode, the ADC will convert
the input measurements as described above, after which the ADC will go into shutdown mode until another
single-shot trigger is generated by writing to the MODE bits. Writing the MODE bits will interrupt and restart
triggered or continuous conversions that are in progress. Although the device can be read at any time, and the
data from the last conversion remains available, the Conversion Ready flag (CNVRF bit in DIAG_ALRT register)
is provided to help coordinate triggered conversions. This bit is set after all conversions and averaging is
completed.
The Conversion Ready flag (CNVRF) clears under these conditions:
• Writing to the ADC_CONFIG register (except for selecting shutdown mode); or
• Reading the DIAG_ALRT Register
While the INA228 device is used in either one of the conversion modes, a dedicated digital engine is calculating
the current, power, charge and energy values in the background as described in Section 7.3.2. In triggered
mode, the accumulation registers (ENERGY and CHARGE) are invalid, as the device does not keep track of
elapsed time. For applications that need critical measurements in regards to accumulation of time for energy and
charge measurements, the device must be configured to use continuous conversion mode, as the accumulated
results are continuously updated and can provide true system representation of charge and energy consumption
in a system. All of the calculations are performed in the background and do not contribute to conversion time.
For applications that must synchronize with other components in the system, the INA228 conversion can be
delayed by programming the CONVDLY bits in CONFIG register in the range between 0 (no delay) and 510 ms.
The resolution in programming the conversion delay is 2 ms. The conversion delay is set to 0 by default.
Conversion delay can assist in measurement synchronization when multiple external devices are used for
voltage or current monitoring purposes. In applications where an time aligned voltage and current measurements
are needed, two devices can be used with the current measurement delayed such that the external voltage and
current measurements will occur at approximately the same time. Keep in mind that even though the internal
time base for the ADC is precise, synchronization will be lost over time due to internal and external time base
mismatch.
7.3.4.1 Low Latency Digital Filter
The device integrates a low-pass digital filter that performs both decimation and filtering on the ADC output data,
which helps with noise reduction. The digital filter is automatically adjusted for the different output data rates and
always settles within one conversion cycle. The user has the flexibility to choose different output conversion time
periods TCT from 50 µs to 4.12 ms. With this configuration the first amplitude notch appears at the Nyquist
frequency of the output signal which is determined by the selected conversion time period and defined as
fNOTCH= 1 / (2 x TCT). This means that the filter cut-off frequency will scale proportionally with the data output
rate as described. Figure 7-3 shows the filter response when the 1.052 ms conversion time period is selected.
INA228
SLYS021 – JANUARY 2021
www.ti.com
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Product Folder Links: INA228



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