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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STPMIC1 датащи(PDF) 106 Page - STMicroelectronics |
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STPMIC1 датащи(HTML) 106 Page - STMicroelectronics |
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106 / 140 page  6.5.8 Interrupt mask registers (INT_MASK_Rx) Table 55. INT_MASK_Rx Name Address 7 6 5 4 3 2 1 0 INT _MASK _R1 0x80 SWOUT _RI SWOUT_ FA VBUS OTG_RI VBUS OTG_FA WKP _RI WKP _FA PKEY _RI PKEY _FA INT _MASK _R2 0x81 BST _OVP BST_OCP SWOUT_ OCP VBUS OTG_OCP BUCK4_ OCP BUCK3_ OCP BUCK2_ OCP BUCK1_ OCP INT _MASK _R3 0x82 SWOUT _SH VBUS OTG_SH LDO6_ OCP LDO5 _OCP LDO4_ OCP LDO3_ OCP LDO2_ OCP LDO1_ OCP INT _MASK _R4 0x83 SWIN _RI SWIN _FA reserved reserved VINLOW_ RI VINLOW_ FA THW _RI THW _FA Address: 0x80 – 0x83 Type: read/write register Default: 0xFF 0x83 Description: interrupt mask registers. Registers are default on RSTn assertion. Reading 1 from the bit means the corresponding interrupt event is masked Refer to Section 6.5.2 Interrupt pending register 1 (INT_PENDING_R1), Section 6.5.3 Interrupt pending register 2 (INT_PENDING_R2), Section 6.5.4 Interrupt pending register 3 (INT_PENDING_R3) and Section 6.5.5 Interrupt pending register 4 (INT_PENDING_R4) about the interrupt description. STPMIC1 Interrupt registers DS12792 - Rev 7 page 106/140 |
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