STPMIC1 datasheet(56/140 Pages) STMICROELECTRONICS

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In case reset happens in ALTERNATE mode, VOUT, ENA and PREG_MODE switch to content of the

[regulator]_MAIN_CR register values.

Figure 59. Reset power-cycle sequence below shows an example of a reset power-cycle on the STPMIC1.

Figure 59. Reset power-cycle sequence

POWER_ON

RSTn

STPMIC1 State

BUCK3 (Rank1)

mask_reset

BUCK1 (Rank2)

POWER_DOWN

RANK0 RANK3 RANK2 RANK1

LDO4 (Rank3)

BUCK2 (Rank0)

rst

Enable Buck2

by I²C

CHECK&

LOAD

POWER_UP

RANK1 RANK2 RANK3

POWER_ON

RSTn Low by AP

27,8ms

mask_reset is a single shot option, cleared by Turn-OFF, POR_VIN and reset.

BUCK3 with mask_reset option set, is not impacted by reset power-cycle.

BUCK1 and LDO4 are powered down and up at their respective rank defined in NVM.

BUCK2, enabled by I2C is power down but not restarted.

5.4.5

Power control modes (MAIN / ALTERNATE)

In order to address implementation of low power platform, the STPMIC1 supports two independent and

configurable modes for POWER_ON state. For all regulators, settings enable (ENA), output voltage (VOUT)

and regulation mode (PREG_MODE) can be defined for each mode. With the following exceptions due to some

regulator specificities:

•

REFDDR provides ENA only

•

LDO3 also provides BYPASS mode bit

•

LDO4 also provides input source selector bits

Default MAIN mode has to be applied to full load applications, typically RUN mode of application processor.

ALTERNATE mode has to be used when the application processor enters low power mode, typically STANDBY

mode. Switch between MAIN and ALTERNATE, can be controlled by the application processor through

PWRCTRL pin.

•

MAIN mode corresponds to “inactive state” of PWRCTRL pin

•

ALTERNATE mode corresponds to “active state” of PWRCTRL pin

PWRCTRL pin detection can be enabled and its polarity configured through respectively PWRCTRL_EN and

PWRCTRL_POL bits in Table 25. MAIN_CR register.

PWRCTRL pin detection is always disabled by default (PWRCTRL_EN bit clear by turn-OFF and reset), as a

consequence POWER_ON mode is always MAIN by default.

In each mode, MAIN or ALTERNATE, the STPMIC1 applies the settings indicated in the regulator (Rx) related

If Buck converter has different output voltage settings between MAIN and ALTERNATE register, a smooth voltage

transition is applied during MAIN to ALTERNATE (and reciprocally) as described in Figure 47. BUCKx dynamic

voltage scaling (DVS).

Please refer to Section 4 Power regulators and switch description for details on voltage scale up and down

procedure for each regulator and switche.

Figure 60. Power mode switch sequence example is an example of the STPMIC1 transition with settings available

in Table 13. MAIN/ALTERNATE switch example configuration and where PWRCTRL is set as active low.

STPMIC1

Feature description

DS12792 - Rev 7

page 56/140

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