STPMIC1 datasheet(50/140 Pages) STMICROELECTRONICS

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5.3

POWER_UP, POWER_DOWN sequence

The STPMIC1 starts and stops regulators following sequential rank procedures called respectively POWER_UP

and POWER_DOWN.

During POWER_UP each regulator is started at one of the 4-rank phase programmed in NVM.

RANK0 means that the regulator is not started.

Default rank is defined:

For BUCKs: Section 6.7.2 NVM BUCK rank shadow register (NVM_BUCKS_RANK_SHR)

For LDO1, 2, 3, 4: Section 6.7.3 NVM LDOs rank shadow register 1 (NVM_LDOS_RANK_SHR1)

For LDO5, 6, REFDDR: Section 6.7.4 NVM LDOs rank shadow register 2 (NVM_LDOS_RANK_SHR2)

Default voltage is defined:

For BUCKs: Section 6.7.5 NVM BUCKs voltage output shadow register (NVM_BUCKS_VOUT_SHR)

For LDO1, 2, 3, 4: Section 6.7.6 NVM LDOs voltage output shadow register 1 (NVM_LDOS_VOUT_SHR1

For LDO5, 6, REFDDR: Section 6.7.7 NVM LDOs voltage output shadow register 2 (NVM_LDOS_VOUT_SHR2)

During POWER_DOWN regulators are shutdown in reverse order than POWER_UP.

Figure 54. STPMIC1 POWER_UP and POWER_DOWN sequence example shows an example of power cycle.

Figure 54. STPMIC1 POWER_UP and POWER_DOWN sequence example

POWER_UP

6.7ms

POWER_ON

RSTn

OFF

Turn_ON condition

CHECK&

LOAD

STPMIC1 State

RANK1 RANK2 RANK3

BUCK3 (Rank1)

ENA bit

BUCK1 (Rank2)

ENA bit

POWER_DOWN

RANK0 RANK3 RANK2 RANK1

LDO4 (Rank3)

ENA bit

BUCK2 (Rank0)

ENA bit

rst

OFF

Enable Buck2

by I²C

Turn_OFF condition

3 ms

100 µs

POWER_UP

The STPMIC1 enables regulators sequentially by 3 ms slots:

RANK1 (BUCK3) -> RANK2 (BUCK1) -> RANK3 (LDO4) regulators, this sequence example is related to the

STPMIC1.

RANK0 regulators (eg BUCK2) are not started.

RSTn is asserted by the STPMIC1 until all regulators on. Then it deasserts RSTn and switches to POWER_ON

as soon as RSTn is deasserted by the application processor (RSTn signal goes high).

POWER_ON:

Regulator state and output voltage are driven by settings to registers MAIN or ALTERNATE control registers.

Those registers are by default initialized with values programmed in NVM and can then be changed through I²C.

In the example, BUCK2 (RANK0) is enabled by I²C.

POWER_DOWN:

The STPMIC1 asserts RSTn and immediately shutdowns RANK0 regulators which may have been started by

software. (BUCK2 in upon example).

Then it disables regulators sequentially in rank reverse order by 3 ms slots:

RANK3 (LDO4) -> RANK2 (BUCK1) -> RANK1 (BUCK3)

STPMIC1

POWER_UP, POWER_DOWN sequence

DS12792 - Rev 7

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