STPMIC1 datasheet(58/140 Pages) STMICROELECTRONICS

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Figure 61. Thermal protection thresholds

TSHDN_Rise

TWRN_Rise

THW_RI Interrupt

TWRN_Fall

TSHDN_Fall

THW_FA Interrupt

T°

5.4.7

Overcurrent protection (OCP)

The STPMIC1 implements protection against short-circuit (SC) or overcurrent (OC) on all regulators output.

The STPMIC1 supports 3 levels of protection described in Table 14. OCP levels below.

Table 14. OCP levels

Protection

level

LOCK_OCP

(NVM)

OCPOFF

[Rx] bit

STPMIC1 behavior

Level 0

This is the default mode.

When SC/OC occurs on regulator Rx :

•

For LDOs and bucks: if current rises above defined tresholds, an automatic

current limitation is activated. Refer to Section 4.2 LDO regulators and

Section 4.4.1 BUCK general description for details

•

For BOOST refer to Section 4.5.1 Boost converter

•

For switches: Refer to PWR_USB_SW and PWR_SW power switches

Note: In case of a sharp increase of the current, the boost overcurrent protection may

react earlier than switch.

•

For all: all interrupts are generated by setting corresponding [Rx]_OCP bit of

INT_PENDING_R2 or INT_PENDING_R3.

(see Section 6.5 Interrupt registers)

The STPMIC1 is in POWER_ON state.

Level 1

By setting OCPOFF[Rx] bit Section 6.3.12 Bucks OCP turn-OFF control register

(BUCKS_OCPOFF_CR) or Section 6.3.13 LDO OCP turn-OFF control register

(LDOS_OCPOFF_CR) registers, an OC on related Rx becomes a turn-OFF condition.

(see Section 5.4.3 Turn-OFF conditions and restart_request

The STPMIC1 starts a POWER_DOWN sequence.

RREQ_EN bit is ignored in case OCP turn-OFF.

The STPMIC1 is in OFF-state until a valid turn-ON condition.

Regulator that caused the OCP turn-OFF can be identified with a

corresponding bit set in overcurrent protection LDO turn-OFF status register

(Section 6.2.3 Overcurrent protection LDO turn-OFF status register

(OCP_LDOS_SR)) or Section 6.2.4 Overcurrent protection buck turn-OFF status

Level 2

NVM_LOCK_OCP (Section 6.7.1 NVM main control shadow register

(NVM_MAIN_CTRL_SHR) bit 0) is set.

This level 2 concerns all regulators. OCPOFF[Rx] bits are ignored.

If SC/OC occurs on any regulators, the STPMIC1 enters POWER_DOWN to finally

goes into LOCK_OCP state

STPMIC1

Feature description

DS12792 - Rev 7

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