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RA4M1 датащи(PDF) 109 Page - Renesas Technology Corp |
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RA4M1 датащи(HTML) 109 Page - Renesas Technology Corp |
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109 / 130 page ![]() R01DS0355EJ0100 Rev.1.00 Page 109 of 130 Oct 8, 2019 RA4M1 Group 2. Electrical Characteristics 2.12.3 Capacitor Split Method [1/3 Bias Method] Note 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON = 1). Note 2. This is a capacitor that is connected between voltage pins used to drive the LCD. C1: A capacitor connected between CAPH and CAPL C2: A capacitor connected between VL1 and GND C3: A capacitor connected between VL2 and GND C4: A capacitor connected between VL4 and GND C1 = C2 = C3 = C4 = 0.47 μF ± 30%. Figure 2.81 LCD reference voltage setup time, voltage boosting wait time, and capacitor split wait time Table 2.66 Internal voltage boosting method LCD characteristics Conditions: VCC = 2.2 V to 5.5 V Parameter Symbol Conditions Min Typ Max Unit Test conditions VL4 voltage*1 VL4 C1 to C4 = 0.47 μF*2 -VCC - V - VL2 voltage*1 VL2 C1 to C4 = 0.47 μF*2 2/3 × VL4 - 0.07 2/3 × VL4 2/3 × VL4 + 0.07 V - VL1 voltage*1 VL1 C1 to C4 = 0.47 μF*2 1/3 × VL4 - 0.08 1/3 × VL4 1/3 × VL4 + 0.08 V - Capacitor split wait time*1 tWAIT 100 - - ms Figure 2.81 MDSET0, MDSET1 VLCON LCDON 01b or 10b 00b tVL1S tVLWT, tWAIT |
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