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RA4M1 датащи(PDF) 81 Page - Renesas Technology Corp |
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RA4M1 датащи(HTML) 81 Page - Renesas Technology Corp |
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81 / 130 page ![]() R01DS0355EJ0100 Rev.1.00 Page 81 of 130 Oct 8, 2019 RA4M1 Group 2. Electrical Characteristics Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle Note 1. The value in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE set to 1. Figure 2.59 IIC bus interface input/output timing IIC (Fast mode) SCL input cycle time tSCL 6 (12) × tIICcyc + 600 -ns Figure 2.59 For all ports except P408, use PmnPFS.DSC R of middle drive. For port P408, use PmnPFS.DSC R1/DSCR of middle drive for IIC fast- mode. SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 -ns SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 -ns SCL, SDA input rise time tSr -300 ns SCL, SDA input fall time tSf -300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA input bus free time (When wakeup function is disabled) tBUF 3 (6) × tIICcyc + 300 -ns SDA input bus free time (When wakeup function is enabled) tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 -ns START condition input hold time (When wakeup function is disabled) tSTAH tIICcyc + 300 - ns START condition input hold time (When wakeup function is enabled) tSTAH 1(5) × tIICcyc + tPcyc + 300 -ns Repeated START condition input setup time tSTAS 300 - ns STOP condition input setup time tSTOS 300 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0- ns SCL, SDA capacitive load Cb -400 pF Table 2.37 IIC timing (2 of 2) Conditions: VCC = 2.7 to 5.5 V Parameter Symbol Min*1 Max Unit Test conditions SDA0 to SDA1 SCL0 to SCL1 VIH VIL tSTAH tSCLH tSCLL P*1 S*1 tSf tSr tSCL tSDAH tSDAS tSTAS tSP tSTOS P*1 tBUF Sr*1 Note 1. S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition. |
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