LTC4230IGN datasheet(16/36 Pages) LINER

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LTC4230

4230f

a start-up check to make sure the supply voltage is above

its 2.3V UVLO threshold (see Time Point 1). If the input

supply voltage is valid, the gate of the external pass

transistor is pulled to ground by the internal 200

µAcurrent

source connected at the GATE

n pin. The TIMER pin is held

low by an internal N-channel pull-down transistor (see

M6, LTC4230 Block Diagram) and the FILTER pin voltage

is pulled to ground by an internal 10

µA current source.

Once VCCn and ON (the ON pin is >1.314V) are valid, the

LTC4230 checks to make sure that GATE

n is OFF (VGATEn

< 0.25V) at Time Point 2. An internal timing circuit is

enabled and the TIMER pin voltage ramps up at the rate

described by Equation 1. At Time Point 3 (the timing period

programmed by CTIMER), the TIMER pin voltage equals

VTMR (1.234V). Next, the TIMER pin voltage ramps down

to Time Point 4 where the LTC4230 performs two checks:

(1) FILTER pin voltage is low (VFILTER < 1.19V) and (2)

FAULT pin voltage is high (VFAULT > 1.284V). If both

conditions are met, the LTC4230 begins a second timing

(soft-start) cycle.

Second Timing (Soft-Start) Cycle

At the beginning of the second timing cycle (Time Point 5),

the LTC4230’s FAST COMP

n is armed and an internal

µA current source working with an internal charge

pump provides the gate drive to the external pass transis-

tor. An expression for the GATE

n voltage slew rate is given

by Equation 3:

Slew Rate

GATE

(3)

where CGATEn = Power MOSFET gate input capacitance

(CISS) for Channel n.

For example, a Si4410DY (a 30V N-channel power MOSFET)

exhibits an approximate CGATE of 3300pF at VGS = 10V. The

LTC4230’s GATE

n voltage rate-of-change (slew rate) for

this example would be:

Slew Rate

GATE

3300

303

The inrush current being delivered to the load while the

GATE

n is ramping is dependent on CLOADn and CGATEn.

Equation 4 gives an expression for the inrush current

during the second timing cycle:

INRUSH

GATE

LOAD

GATE

== µ

••

(4)

For example, if CGATEn = 3300pF and CLOADn = 2000µF, the

inrush current charging CLOADn is:

INRUSH =µ

2000

0 0033

606

•

(5)

At Time Point 7, the output voltage trips FBCOMP

n’s

threshold, signaling an output voltage “power good” con-

dition. RESET 2 and RESET 3 pull high. At Time Point 8,

RESET 1 asserts high, SLOW COMP is armed and the

LTC4230 enters a fault monitor mode.

SOFT-START WITH CURRENT LIMITING

During the second timing cycle, the inrush current is

described by Equation 4. Note that there is a one-to-one

correspondence in the inrush current to CLOADn. If the

inrush current is large enough to cause a voltage drop

greater than 50mV across the sense resistor, an internal

servo loop controls the operation of the 10

µA current

source at the GATE

n pin to regulate the load current to:

LIMIT SOFTSTART

SENSE

()

(6)

For example, the inrush current is limited to 5A when

RSENSEn = 0.01Ω.

In this fashion, the inrush current is controlled and CLOADn

is charged up slowly during the soft-start cycle.

The timing diagram in Figure 6 illustrates the operation of

the LTC4230 in a normal power-up sequence with limited

inrush current as described by Equation 6. At Time Point 5,

the GATE pin voltage begins to ramp indicating that the

power MOSFET is beginning to charge CLOADn. At Time

Point 5, the inrush current causes a 50mV voltage drop

across RSENSEn and an internal servo loop engages, limit-

ing the inrush current to a fixed level. At Time Point 6, the

GATE

n pin voltage continues to ramp as CLOADn charges

until VOUTn reaches its final value. The charging current

APPLICATIO S I FOR ATIO

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