L9942

5 SPI - Control and Status Registers

25/37

5.8.2

SPI communication monitoring

At the rising edge of the CSN signal the contents of the shift register will be transferred to the

selected data register. A counter monitors proper SPI communication. It counts rising edges at

pin CLK. The writing to the register is only enabled if exactly 16 bits are transmitted within one

communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame

the complete frame will be ignored. This safety function is implemented to avoid an activation of

the output stages by a wrong communication frame. SPI communication can be checked by

loading a command twice and then answer at pin DO must be same.

Note:

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel

operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended.

5.8.3

PWM monitoring for stall detection

Control registers 4, 5, and 3 contain bits D0-D7, use for setting a stall detection threshold. The

value in this set of bits determine the minimum time for current rise over one quadrant of motor

driving. D7-D0 is compared with the sum of the rise times over one quadrant. When the sum is

less than the value stored in D7-D0 the ST bit (register6 bit 8) is set to a logic “1”.

The PWM pin reflects the PWM control signal of the load current in bridge A. This is so after

power on when the SST bit (register 6, bit11) is reset to a logic “0”. If this bit is set to a logical

“1” then status of the ST bit 8 is mirrored to pin PWM. This provides stall detection without the

need of reading register 6 through the SPI bus.