5 SPI - Control and Status Registers

L9942

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5.7

Status Register7

The meaning of the different bits is as follows:

5.8

Auxiliary logic blocks

5.8.1

Fault Condition

Logical level at pin D0 represents fault condition. It is valid from first high to low edge of signal

CLK up to transfer of data bit D12. Fault bit is an logical OR of:

Control and Status Register 6 bit 5 and 6 for Open Load, bit7 reference current failure

(RERR) and

Control and Status Register 7 bit 0 to bit 7 for Overcurrent, bit 8 and 9 failure at VS

(UV,OV) and

bit 10 and bit 11 during high temperature (TW,TSD)

FT

SST

This bit specifies output PWM to reflect same logical level like bit ST.

CLR6

This bit resets all bits to 0 in register 6.

Bit

CLR

Temperature

VS Monitor

Overcurrent

12

11

10

9

8

7

6

5

4

3

2

1

0

Access

r w

r

r

r

r

r

r

r

r

r

r

r

r

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

Name

CLR7

TSD

TW

OV

UV

HSB2

HSB1

LSB2

LSB1

HSA2

HSA1

LSA2

LSA1

bit7 ... bit0

These bits indicate overcurrent in each lowside or highside power transistor.

1

overcurrent failure I > 2A

OV UV

These bits indicates failure at VS ( See also parameter

Table 8)

01

Voltage at pin VS is too low.

10

Voltage at pin VS is too high.

TSD TW

These bits indicates temperature failure ( See also parameter

Table 6)

01

Only for information set at temperature warning threshold.

10

In case of thermal shutdown all bridges are switched off. It has to reset by bit CLR7.

CLR7

This bit resets all bits to 0 in register7.