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L9942 датащи(PDF) 23 Page - STMicroelectronics |
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L9942 датащи(HTML) 23 Page - STMicroelectronics |
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23 / 37 page ![]() L9942 5 SPI - Control and Status Registers 23/37 The meaning of the different bits is as follows: 5.5 Counter and Profile (Register 4 and Register 5) The meaning of the different bits is as follows: 5.6 Control, Status and Profile Register 6 The meaning of the different bits is as follows: I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed. See also parameter Table 12 DT1 DT0 These bits are for threshold value in counter of active time during signal PWM. NPWM This bit switches internal PWM signal of bridge A to pin PWM if it is set to 0, otherwise pin is in high resistance status. (T5 T4 T3) These bits are used in test mode only. Bit Current Profile 5 (7) PWM Counter Current Profile 4 (6) 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r w r w r w r w r w r w r w r w r w r w r w r w r w Reset 0 0 0 0 00 0 0 0 0 00 0 Name I4 I3 I2 I1 I0 D4(7) D3(6) D2(5) I4 I3 I2 I1 I0 I4 I3 I2 I1 I0 These bits are loadedneeded. in register1 DAC Phase A or B if needed. See also parameter Table 12 D4 D3 D2 (register4) These bits are for threshold value in counter of active time during signal PWM. LSB and next value are set in register3 by D0 and D1. D7 D6 D5 (register5) CLR ST (PWM) Filter Freq ST REF ERR Openload Current Profile 8 Bit 12 11 10 9 8 7 6 5 4 3 2 1 0 Access r w r w r w r w r r r r r w r w r w r w r w Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 Name CLR6 SST FT FRE ST RERR OB OA I4 I3 I2 I1 I0 I4 I3 I2 I1 I0 These bits are loaded in register1 DAC Phase A or B if needed See also parameter Table 12 OB OA These bits indicate openload at bridges RERR This bit indicates if reference current is OK (150uA <IREF < 250uA), then is RERR=0. ST This bit indicates stall detection. FRE This bit sets frequency of PWM cycle. FRE=1 frequency 20kHz, FRE=0 frequency 30kHz |
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