AGLP030 datasheet(27/128 Pages) ACTEL

27 / 128 page

IGLOO PLUS Low Power Flash FPGAs

Re vi s i on 11

2 - 13

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on

page 2-14.

FCLK is the global clock signal frequency.

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on

page 2-14.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on

page 2-14.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.

1 is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-14.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

2 is the RAM enable rate for read operations.

FWRITE-CLOCK is the memory write clock frequency.

3 is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on

page 2-14.

PLL Contribution—PPLL

PPLL = PDC4 + PAC13 *FCLKOUT

FCLKOUT is the output clock frequency.

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