PCF8545ATT datasheet(13/54 Pages) NXP

13 / 54 page

PCA85233

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 5 — 12 November 2018

13 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives

the provision for preparing display information in an alternative bank and to be able to

switch to it once it is assembled.

7.3.6 Input bank selector

The input bank selector loads display data into the display RAM in accordance with the

selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode

or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

Table 9). The input bank selector functions independently to the output bank selector.

7.4 Initialization

At power-on the status of the I2C-bus and the registers of the PCA85233 is undefined.

Therefore the PCA85233 should be initialized as quickly as possible after power-on to

ensure a proper bus communication and to avoid display artifacts. The following

instructions should be accomplished for initialization:

7.4.1 Device initialization

At power-on the status of the I2C-bus communication interface is undefined since this

device doesn’t have POR which was removed to improve the ESD performance. A START

and STOP condition with dummy byte in-between must be sent after every power reset to

set up the I2C-bus communication interface.

• I2C-bus (see Section 8) initialization

– generating a START condition

– sending 0h (1 byte) and ignoring the acknowledge – Note, this is not the device

address but just a dummy byte of all zeros

– generating a STOP condition

7.4.2 Device setup

At power-on the status of the display and configuration registers are undefined and need

to be set up to properly display information on the LCD display. After the I2C-bus interface

is initialized as discussed in Section 7.4.1 set up the device using these register settings

• Mode-set command (see Table 6), setting

– bit E = 0

– bit B to the required LCD bias configuration

– bits M[1:0] to the required LCD drive mode

• Load-data-pointer command (see Table 7), setting

– bits P[4:0] to 0h (or any other required address)

• Device-select command (see Table 8), setting

– bits A[1:0] to the required hardware subaddress (for example, 0h)

• Bank-select command (see Table 9), setting

– bit I to 0

– bit O to 0

• Blink-select command (see Table 10), setting

PCF8545ATT датащи(PDF) 13 Page - NXP Semiconductors

PCF8545ATT датащи(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

датащи скачать

ссылки URL