PCF8545ATT datasheet(8/54 Pages) NXP

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PCA85233

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Product data sheet

Rev. 5 — 12 November 2018

8 of 54

NXP Semiconductors

PCA85233

Automotive 80 × 4 LCD driver for low multiplex rates

An additional feature is for an arbitrary selection of LCD segments to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. By means of the output bank selector, the displayed RAM

banks are exchanged with alternate RAM banks at the blink frequency. This mode can

also be specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can blink by selectively changing the display RAM data at fixed time

intervals.

If the entire display can blink at a frequency other then the typical blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 6).

7.3 Display RAM

The display RAM is a static 80

 4 bit RAM which stores LCD data.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD segments/elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;

similarly, a logic 0 indicates the off-state.

The display RAM bit map, Figure 4, shows rows 0 to 3 which correspond with the

backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment

outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second,

third and fourth row of the display RAM are time-multiplexed with BP0,

BP1, BP2, and BP3 respectively.

Table 12.

Blink frequencies

Blink mode

Operating mode ratio

Blink frequency with respect to fclk (typical)

Unit

fclk = 3.600 kHz

fclk = 5.280 kHz

off

blinking off

14.7

6.9

22.3

3.4

31.2

1.7

clk

768

---------

clk

1536

------------

clk

3072

------------

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