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PCF8545ATT датащи(PDF) 33 Page - NXP Semiconductors

номер детали PCF8545ATT
подробное описание детали  Automotive 80 횞 4 LCD driver for low multiplex rates
PDF  54 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF8545ATT датащи(HTML) 33 Page - NXP Semiconductors

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PCA85233
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 5 — 12 November 2018
33 of 54
NXP Semiconductors
PCA85233
Automotive 80 × 4 LCD driver for low multiplex rates
13. Dynamic characteristics
Table 21.
Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +105 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock
Internal: output pin CLK
fclk
clock frequency
FF = VDD
[1][2] 2630
3600
4680
Hz
FF = VSS
[1][2] 3855
5280
6865
Hz
ffr
frame frequency
FF = VDD
-
150
-
Hz
FF = VSS
-
220
-
Hz
f
fr
frame frequency variation
FF = VDD; see Figure 22
110
150
195
Hz
FF = VSS; see Figure 22
161
220
286
Hz
External: input pin CLK
fclk(ext)
external clock frequency
[2] 800
-
7000
Hz
tclk(H)
HIGH-level clock time
90
-
-
s
tclk(L)
LOW-level clock time
90
-
-
s
Synchronization: input pin SYNC
tPD(SYNC_N) SYNC propagation delay
-
30
-
ns
tSYNC_NL
SYNC LOW time
1
-
-
s
Outputs: pins BP0 to BP3 and S0 to S79
tPD(drv)
driver propagation delay
VLCD = 5 V
-
-
30
s
I2C-bus: timing[3]
Pin SCL
fSCL
SCL clock frequency
-
-
400
kHz
tHIGH
HIGH period of the SCL
clock
0.6
-
-
s
tLOW
LOW period of the SCL
clock
1.3
-
-
s
Pin SDA
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns



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