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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9082 датащи(PDF) 13 Page - Analog Devices |
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AD9082 датащи(HTML) 13 Page - Analog Devices |
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13 / 33 page  Data Sheet AD9082 Rev. A | Page 13 of 33 Parameter Min Typ Max Unit WORST HD3 fIN = 253 MHz −80.0 dBFS fIN = 450 MHz −78.3 dBFS fIN = 900 MHz −70.8 dBFS fIN = 1800 MHz −66 dBFS fIN = 2700 MHz −70.8 dBFS fIN = 3600 MHz −69.2 dBFS fIN = 4500 MHz −64.3 dBFS fIN = 5400 MHz −62 dBFS WORST OTHER, EXCLUDING HD2 OR HD3 HARMONIC fIN = 253 MHz −85.3 dBFS fIN = 450 MHz −81.4 dBFS fIN = 900 MHz −76.5 dBFS fIN = 1800 MHz −72.1 dBFS fIN = 2700 MHz −68.5 dBFS fIN = 3600 MHz −65.9 dBFS fIN = 4500 MHz −64.2 dBFS fIN = 5400 MHz −62.7 dBFS TWO-TONE IMD3, Input Amplitude 1 (AIN1) = Input Amplitude 2 (AIN2) = −7 dBFS Input Frequency 1 (fIN1) = 890 MHz, Input Frequency 2 (fIN2) = 910 MHz fIN1 = 1780 MHz, fIN2 = 1820 MHz −78.9 dBFS fIN1 = 2680 MHz, fIN2 = 2720 MHz −75 dBFS fIN1 = 3560 MHz, fIN2 = 3640 MHz −73.2 dBFS fIN1 = 5360 MHz, fIN2 = 5440 MHz −64.2 dBFS ANALOG BANDWIDTH3 8 GHz 1 Noise density is measured at a low analog amplitude and/or frequency where timing jitter does not degrade noise floor. 2 Noise figure is based on a nominal full-scale input power of 4.5 dBm with an input span of 1.5 V p-p and RIN = 100 Ω. 3 Analog input bandwidth is the bandwidth of operation in which the full-scale input frequency response rolls off by −3 dB based on a de-embedded model of the ADC extracted from the measured frequency response on evaluation board. This bandwidth requires optimized matching network to achieve this upper bandwidth. TIMING SPECIFICATIONS For the minimum and maximum values, TJ = −40°C to +120°C and ±5% of nominal supply, unless otherwise noted. Table 11. Parameter Symbol Test Conditions/Comments Min Typ Max Unit SERIAL PORT INTERFACE (SPI) WRITE OPERATION Maximum SCLK Clock Rate fSCLK, 1/tSCLK 33 MHz SCLK Clock High tPWH SCLK = 33 MHz 5 ns SCLK Clock Low tPWL SCLK = 33 MHz 5 ns SDIO to SCLK Setup Time tDS 4 ns SCLK to SDIO Hold Time tDH 4 ns CSB to SCLK Setup Time tS 4 ns SCLK to CSB Hold Time tH 4 ps |
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