AD9082 datasheet(32/33 Pages) AD

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AD9082

Data Sheet

Rev. A | Page 32 of 33

THEORY OF OPERATION

The AD9082 is a highly integrated, 28 nm, RF, MxFE featuring

four 16-bit, 12 GSPS DAC cores and two 12-bit, 6 GSPS ADC

cores (see Figure 1). The DAC core is based on a current

segmentation architecture providing a differential complementary

current output with an adjustable full-scale output (IOUTFS) range

of 7 mA to 40 mA. The ADC core is based on a proprietary

interleaved architecture that suppresses residual interleaving

spurious products into the noise floor. To enable wide bandwidth

operation, a high linearity 100 Ω differential buffer with overload

protection is used to isolate the ADC core from the RF ADC

driver source. An on-chip clock multiplier can be used to

synthesize the RF DAC and ADC clocks or, alternatively,

an external clock can be applied.

Flexible transmit and receive DSP paths are available to up and

down sample the desired intermediate frequency (IF) or RF

signal(s) to manageable data interface rates aligned with

bandwidth requirements. The transmit and receive DSP paths are

symmetric and consist of four coarse digital upconversion (DUC)

and digital downconversion (DDC) blocks in the main datapath

along with eight fine DUC and DDC blocks in the channelizer

datapath. Each block includes a 48-bit NCO configurable for

integer or fractional mode of operation. The channelizer

datapath enables an efficient implementation to support

multiband applications where up to eight RF bands can be

supported. Each of the DUC and DDC blocks are bypassable

and offer flexible interpolating and decimation factors. The

NCO in each block also supports coherent frequency hopping.

Additional features are also included in the receive and

transmit datapaths as well as elsewhere to facilitate system

integration. Both datapaths include adjustable delay lines to

compensate for mismatch in channel delay paths that may occur

external to the device. The transmit datapath includes digital gain

control, fine delay adjust, and power amplifier protection to

simplify DPD integration in a multiband transmitter. The receive

path includes a flexible programmable 192-tap finite impulse

response (PFIR) filter. The filter can be allocated across one or

more ADCs for receive equalization with support for four

different profiles. These profiles can be selected using the

GPIOx pins. The receive datapath also includes a fast and slow

signal detection capability in support of automatic gain control

(AGC). Transmit and receive data formatting can be real or

complex with resolutions of 8, 12, 16, and 24 bits depending on

the JESD204B or the JESD204C mode. The AD9082 also allows

complete bypass of the transmit and receive DSP paths enabling

Nyquist operation.

The device also supports fast frequency hopping via GPIOx and a

low latency digital loopback capability. An on-chip TMU is also

included and can be used as part of a thermal management

solution. Power savings option in support of time division

duplex (TDD) applications are included.

A 16-lane JESD204 transceiver port is available to support the

high data throughput rates on the receive and transmit datapaths.

Eight SERDES lanes are designated for the transmit datapaths,

while the other 8 lanes are designated for the receive datapaths with

the option to support two links. The transceiver port supports

JESD204C up to 16.22 GSPS or JESD204B up to 15.5 GSPS lane

rates. The JESD204 data link layer is highly flexible allowing

optimization of the lane count (or rate) required to support a

target throughput rate. Internal synchronization for deterministic

latency and phase alignment as well as multichip synchronization

are possible via an external alignment signal (SYSREF).

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