May 2005

ASM2I99447

rev 0.3

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

8 of 14

Notice: The information in this document is subject to change without notice.

CCLK

GND

GND

GND

GND

The pin-to-pin skew is defined as the worst case

difference in propagation between any similar delay path

within a single device

CCLK

GND

GND

GND

The time from the output controlled edge to the

non-controlled edge, divided by the time output

controlled edge, expressed as a percentage.

Figure 9. Output Duty Cycle (DC)

2.4

1.8V

0.5

0.6V

Figure 10. Output Transition Time Test Reference

The variation in cycle time of a single between adjacent

cycles, over a random sample of adjacent cycle pairs

CCLK

PCLK

GND

GND

CLK_STOP