May 2005

ASM2I99447

rev 0.3

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

4 of 14

Notice: The information in this document is subject to change without notice.

1

Symbol

5Characteristics

Min

Typ

Max

Unit

Condition

Input Frequency

0

350

MHz

Output Frequency

0

350

MHz

Reference Input Pulse Width

1.4

nS

CCLK0, CCLK1 Input Rise/Fall Time

1.0

2

nS

0.8 to 2.0V

Propagation Delay

CCLK0 or CCLK1 to any Q

1.3

3.3

nS

Output Disable Time

11

nS

Output Enable Time

11

nS

Setup Time

CCLK0 or CCLK1 to CLK_STOP

3

0.0

nS

Hold Time

CCLK0 or CCLK1 to CLK_STOP

3

1.0

nS

Output-to-Output Skew

150

pS

Device-to-Device Skew

2.0

nS

DCQ

Output Pulse Skew

4

Output Duty Cycle

fQ<170

MHz

45

50

300

55

pS

%

Output Rise/Fall Time

0.1

1.0

nS

0.55 to 2.4V

Cycle-to-cycle jitter

RMS (1

σ)

TBD

pS

Note: 1. AC characteristics apply for parallel output termination of 50

2. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,

output duty cycle and maximum frequency specifications.

3. Setup and hold times are referenced to the falling edge of the selected clock signal input.

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input High Voltage

1.7

V

LVCMOS

Input Low Voltage

-0.3

0.7

V

LVCMOS

Output High Voltage

1.8

V

1

Output Low Voltage

0.6

V

Output Impedance

19

Ω

Input Current

2

±300

mA

Maximum Quiescent Supply Current

3

2.0

mA

Note: 1.The ASM2I99447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to

2. Inputs have pull-down or pull-up resistors affecting the input current.

3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.