May 2005

ASM2I99447

rev 0.3

3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer

5 of 14

Notice: The information in this document is subject to change without notice.

1

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input Frequency

0

350

MHz

Output frequency

0

350

MHz

Reference Input Pulse Width

1.4

nS

CCLK0, CCLK1 Input Rise/Fall Time

1.0

2

nS

0.7 to 1.7V

Propagation Delay

CCLK0 or CCLK1 to any Q

1.7

4.4

nS

Output Disable Time

11

nS

Output Enable Time

11

nS

Setup Time

CCLK0 or CCLK1 to CLK_STOP

3

0.0

nS

Hold Time

CCLK0 or CCLK1 to CLK_STOP

3

1.0

nS

Output-to-Output Skew

150

pS

Device-to-Device Skew

2.7

nS

Output Pulse Skew

4

Output Duty Cycle

45

50

200

55

pS

%

Output Rise/Fall Time

0.1

1.0

nS

0.6 to 1.8V

Cycle-to-cycle jitter

RMS (1

σ)

TBD

pS

2. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse

width, output duty cycle and maximum frequency specifications.

3. Setup and hold times are referenced to the falling edge of the selected clock signal input.