LIS2DW12 datasheet(29/66 Pages) STMICROELECTRONICS

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Slave

SAK

DATA

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred

per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive

another complete byte of data until it has performed some other function, it can hold the clock line, SCL low to

force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and

releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive

because it is performing some real-time function) the data line must be left high by the slave. The master can then

abort the transfer. A low-to-high transition on the SDA line while the SCL line is high is defined as a STOP

condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.

In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge.

6.2

SPI bus interface

The LIS2DW12 SPI is a bus slave. The SPI allows writing to and reading from the registers of the device.

The serial interface interacts with the application using 4 wires: CS, SPC, SDI and SDO.

Figure 12. Read and write protocol

SPC

SDI

SDO

AD5 AD4 AD3 AD2 AD1 AD0

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

AD6

CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and

goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high

when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those

lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC.

Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case

of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at

the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling

edge of SPC just before the rising edge of CS.

bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is

read. In latter case, the chip will drive SDO at the start of bit 8.

bit 1-7: address AD(6:0). This is the address field of the indexed register.

bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).

bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).

In multiple read/write commands additional blocks of 8 clock periods will be added. When the CTRL2 (21h)

(IF_ADD_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the CTRL2

(21h) (IF_ADD_INC) bit is ‘1’, the address used to read/write data is increased at every block.

The function and the behavior of SDI and SDO remain unchanged.

LIS2DW12

SPI bus interface

DS11811 - Rev 8

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