LPC55S2X datasheet(43/126 Pages) NXP

43 / 126 page

LPC55S2x/LPC552x

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Product data sheet

Rev. 1.8 — 4 March 2020

43 of 126

NXP Semiconductors

LPC55S2x/LPC552x

32-bit ARM Cortex-M33 microcontroller

7.10 Protected Flash Region (PFR)

The protected flash region is available to configure secure boot, debug authentication,

read UUID, store PUF in key store area, and user defined fields available for specific data

storage.

7.11 Memory mapping

7.12 AHB multilayer matrix

The LPC55S2x/LPC552x uses a multi-layer AHB matrix to connect the CPU buses and

other bus masters to peripherals in a flexible manner that optimizes performance by

allowing peripherals that are on different slave ports of the matrix to be accessed

simultaneously by different bus masters. The device block diagram in Figure 3 shows

details of the available matrix connections.

7.13 Memory Protection Unit (MPU)

CPU has a memory protection unit (MPU) that provides fine grain memory control,

enabling applications to implement security privilege levels, separating code, data and

stack on a task-by-task basis. Such requirements are critical in many embedded

applications.

The MPU register interface is located on the CPU private peripheral bus and is described

in detail in Ref 1 “Cortex-M33 DEBUG”

7.14 Links to specific memory map descriptions and tables:

• Section 7.15 “Memory map overview”

• Section 7.16 “APB peripherals”

• Section 7.17 “AHB peripherals”

7.15 Memory map overview

Table 5 gives a more detailed memory map as seen by the Cortex-M33. The purpose of

the four address spaces for the shared RAMs is outlined at the beginning of this chapter.

The details of which shared RAM regions are on which AHB matrix slave ports can be

seen here.

Table 5.

Memory map overview

AHB

port

Start address

End address

Function [1]

0x0000 0000

0x0007 FFFF

Flash memory, on CM33 code bus.

0x0300 0000

0x0301 FFFF

Boot ROM, on CM33 code bus.

0x0400 0000

0x0400 7FFF

SRAM X on CM33 code bus, 32 KB. SRAMX_0 (0x1400 0000 to 0x1400

0FFF) and SRAMX_1 (0x1400 4000 to 0x1400 4FFF) are used for

Casper (total 8 KB). If CPU retention used in power-down mode,

SRAMX_2 (0x1400 6000 to 0x1400 65FF) is used (total 1.5 KB) by

default in power API and this is user configurable within SRAMX_2 and

SRAMX_3.

0x2000 0000

0x2000 FFFF

SRAM 0 on CM33 data bus, 64 KB.

0x2001 0000

0x2001 FFFF

SRAM 1 on CM33 data bus, 64 KB.

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