LPC55S2X datasheet(2/126 Pages) NXP

2 / 126 page

LPC55S2x/LPC552x

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.8 — 4 March 2020

2 of 126

NXP Semiconductors

LPC55S2x/LPC552x

32-bit ARM Cortex-M33 microcontroller



PRINCE module for real-time encryption of data being written to on-chip flash and

decryption of encrypted flash data during read to allow asset protection, such as

securing application code, and enabling secure flash update.



On-chip ROM bootloader supports:



Booting of images from on-chip flash



Supports CRC32 image integrity checking.



Supports flash programming through In System Programming (ISP) commands

over following interfaces: USB0/1 interfaces using HID Class device, UART

interface (Flexcomm 0) with auto baud, SPI slave interfaces (Flexcomm 3 or 9)

using mode 3 (CPOL = 1 and CPHA = 1), and I2C slave interface (Flexcomm 1)



ROM API functions: Flash programming API, Power control API, and Secure

firmware update API using NXP Secure Boot file format, version 2.0 (SB2 files).



Supports booting of images from PRINCE encrypted flash regions.



Support NXP Debug Authentication Protocol version 1.0 (RSA-2048) and 1.1

(RSA-4096).



Supports setting a sealed part to Fault Analysis mode through Debug

authentication.



Secure Boot support:



Uses RSASSA-PKCS1-v1_5 signature of SHA256 digest as cryptographic

signature verification.



Supports RSA-2048 bit public keys (2048 bit modulus, 32-bit exponent).



Supports RSA-4096 bit public keys (4096 bit modulus, 32-bit exponent).



Uses x509 certificate format to validate image public keys.



Supports up to four revocable Root of Trust (RoT) or Certificate Authority keys,

Root of Trust establishment by storing the SHA-256 hash digest of the hashes of

four RoT public keys in protected flash region (PFR).



Supports anti-rollback feature using image key revocation and supports up to 16

Image key certificates revocations using Serial Number field in x509 certificate.



Serial interfaces:



Flexcomm Interface contains up to nine serial peripherals (Flexcomm Interface 0-7

and Flexcomm Interface 8). Each Flexcomm Interface (except flexcomm 8, which

is dedicated for high-speed SPI) can be selected by software to be a USART, SPI,

I2C, and I2S interface. Each Flexcomm Interface includes a FIFO that supports

USART, SPI, and I2S. A variety of clocking options are available to each Flexcomm

Interface, including a shared fractional baud-rate generator, and time-out

feature.Flexcomm interfaces 0 to 7 each provide one channel pair of I2S.



I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to

1Mbit/s and with multiple address recognition and monitor mode. Two sets of true

I2C pads also support high-speed Mode (3.4 Mbit/s) as a slave.



USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA

controller supporting crystal-less operation in device mode using software library

example in technical note (TN00063).



USB 2.0 high-speed host/device controller with on-chip high-speed PHY.



Digital peripherals:



DMA0 controller with 23 channels and up to 22 programmable triggers, able to

access all memories and DMA-capable peripherals.



DMA1 controller with 10 channels and up to 15 programmable triggers, able to

access all memories and DMA-capable peripherals.

LPC55S2X датащи(PDF) 2 Page - NXP Semiconductors

LPC55S2X датащи(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL