LPC55S2X datasheet(36/126 Pages) NXP

36 / 126 page

LPC55S2x/LPC552x

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Product data sheet

Rev. 1.8 — 4 March 2020

36 of 126

NXP Semiconductors

LPC55S2x/LPC552x

32-bit ARM Cortex-M33 microcontroller

[1]

PU = input mode, pull-up enabled (pull-up resistor pulls pin up towards VDD). PD = input mode, pull-down enabled (pull-down resistor

pulls pin down towards VSS). Z = high impedance; pull-up, pull-down, and input disabled. AI = analog input. I = input. O = output. I/O =

input/output. Reset state reflects the pin state at reset without boot code operation. For termination on unused pins, see Section 6.1.1

“Termination of unused pins”.

[2]

Pad with programmable glitch filter; provides digital I/O functions with TTL levels and hysteresis; normal drive strength. Pulse width of

spikes or glitches suppressed by input filter is from 3 ns to 16 ns (simulated value).

[3]

True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode

Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not

disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

[4]

Pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an

analog input, the digital section of the pin is disabled.

[5]

Reset pad with glitch filter and hysteresis. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to

20 ns (simulated value)

[6]

Transparent analog pad.

[7]

Optional bypass mode is supported, xtal32M_P can be driven by an external clock with restrictions in terms of drive level.

[8]

The corresponding VBUS must be connected to supply voltage when using the USB peripheral. VBUS is 5V tolerant.

VBAT_DCDC

N13

49, 50 [9]

Supply of DCDC output stage. DCDC core supply

(references and regulation stages).

VBAT_ PMU

M13

[9]

Analog supply.

VDD

8; 16;

43; 54

M1; A5;

A9;

A13

15;

25;

44;

63;

69;75;

84;

95;

100

Single 1.8 V to 3.6 V power supply powers I/Os.

VDD_PMU

Core supply. For applications with DCDC converter,

VDD_PMU and FB are tied at PCB level.

VDDA

Analog supply voltage. At PCB level, has to be tied to main

supply (VBAT_PMU, VBAT_DCDC)

VREFN

ADC negative reference voltage.

VREFP

ADC positive reference voltage.

VSS

exposed

pad

N1; B5;

B9;

B13

expos

pad

Ground.

VSS_DCDC

N12,

M12

46, 47

Star ground connection is managed to PCB ground plane.

VSS_PMU

M11

Star ground connection is managed to PCB ground plane.

VSSA

Analog ground.

XTAL32K_N

J12

RTC oscillator output.

XTAL32K_P

J13

RTC oscillator input.

XTAL32M_N

[7]

Main oscillator output.

XTAL32M_P

[7]

Main oscillator input.

Table 3.

Pin description …continued

Symbol

Description

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