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K32L3A датащи(PDF) 12 Page - NXP Semiconductors

номер детали K32L3A
подробное описание детали  72 MHz Arm짰 Cortex짰-M0/M4F Dual Core Microcontroller with up to 1280 KB Flash and 384 KB SRAM
PDF  162 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

K32L3A датащи(HTML) 12 Page - NXP Semiconductors

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Boot Sequence
START
RESET==0
SCG is enabled
Required clocks
are enabled
Flash controller is
initialized
Flash option is read
and stored in
FTFE_FOPT
Is
BOOT_MODE/
BOOT_CLK
==11?
Modify clock
divider
Core option is
read and stored in
FOPT[BOOTCORESEL]
Enable selected
boot core
complete flash
initialization
Release
RESET
Release device
reset
Set up
Stack Pointer
Set up
Program Counter
Set up
Link Register
Enable boot
core clock
FOPT
[BOOT_PIN]
==0?
Is
NMI = 0
?
FTFE_FOPT
[BOOT_SRC]
==?
Processor boot from
ROM
Processor boots
from Flash
Yes
Yes
00
Yes
No
No
10/11
No
Figure 2. Boot sequence
Blank chips default to boot from ROM and remap the vector table to ROM base
address, otherwise, it remaps to flash address.
If booting from ROM, the device executes in boot loader mode.
2.1.7 ROM bootloader
The Kinetis bootloader is the program residing in the on-chip read-only memory
(ROM) of a Kinetis microcontroller device. There is hardware logic in place at boot
time that either starts execution of an embedded image available on the internal flash
memory, or starts the execution of the Kinetis Bootloader from on-chip ROM.
Features supported by the Kinetis Bootloader in Kinetis ROM:
• Supports USB, LPI2C, LPSPI, and LPUART peripheral interfaces
Overview
12
K32L3A, Rev. 1, 09/2019
NXP Semiconductors



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