STM8S datasheet(332/467 Pages) STMICROELECTRONICS

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Universal asynchronous receiver transmitter (UART)

RM0016

332/467

DocID14587 Rev 14

Figure 117. Start bit detection

Note:

If the sequence is not complete, the start bit detection aborts and the receiver returns to the

idle state (no flag is set), where it waits for a falling edge.

If only 2 out of the 3 bits are at 0 (sampling on the 3rd, 5th and 7th bits or sampling on the 8th,

9th and 10th bits), the start bit is validated but the NF noise flag bit is set.

The start bit is confirmed if the last 3 samples are at 0 (sampling on the 8th, 9th, and 10th

bits.

Character reception

During an UART reception, data shifts in least significant bit first through the UART_RX pin.

In this mode, the UART_DR register consists of a buffer (RDR) between the internal bus

and the received shift register (see Figure 2).

Procedure:

Program the M bit in UART_CR1 to define the word length.

Program the number of stop bits in UART_CR3.

Select the desired baud rate by programming the baud rate registers in the following

order:

UART_BRR2

UART_BRR1

Set the REN bit UART_CR2. This enables the receiver which begins searching for a

start bit.

Falling edge

detection

11 12131415 16

6/16

7/16

At least 2 bits

out of 3 at 0

At least 2 bits

out of 3 at 0

One-bit time

Conditions

to validate

the start bit

Real

sample

clock

Ideal

sample

clock

RX line

RX state

Idle

Start bit

Sampled values

ai15471b

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