STM8S datasheet(311/467 Pages) STMICROELECTRONICS

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RM0016

Inter-integrated circuit (I2C) interface

319

Bit 2 BTF: Byte transfer finished (7)(8)

0: Data byte transfer not done

1: Data byte transfer succeeded

– Set by hardware when NOSTRETCH=0 and:

–

In reception when a new byte is received (including ACK pulse) and DR has not been read

yet (RXNE=1).

–

In transmission when a new byte should be sent and DR has not been written yet (TXE=1).

– Cleared by software reading SR1 followed by either a read or write in the DR register or by hardware

after a start or a stop condition in transmission or when PE=0.

Bit 1 ADDR: Address sent (master mode)/matched (slave mode) (8)(9)

This bit is cleared by software reading SR1 register followed reading SR3, or by hardware when PE=0.

– Address matched (Slave)

0: Address mismatched or not received.

1: Received address matched.

–

Set by hardware as soon as the received slave address matched with the OAR registers

content or a general call or a SMBus is recognized. (when enabled depending on

configuration).

– Address sent (Master)

0: No end of address transmission

1: End of address transmission

–

For 10-bit addressing, the bit is set after the ACK of the 2nd byte.

–

For 7-bit addressing, the bit is set after the ACK of the byte.

Note: ADDR is not set after a NACK reception

Bit 0 SB: Start bit (Master mode) (8)

0: No Start condition

1: Start condition generated.

–

Set when a Start condition generated.

–

Cleared by software by reading the SR1 register followed by writing the DR register, or by

hardware when PE=0

1. The interrupt will be generated when DR is copied into shift register after an ACK pulse. If a NACK is received, copy is not

done and TXE is not set.

2. The interrupt will be generated when Shift register is copied into DR after an ACK pulse.

3. RXNE is not set in case of ARLO event.

4. The STOPF bit is not set after a NACK reception.

5. It is recommended to perform the complete clearing sequence (READ SR1 then WRITE CR2) after STOPF is set. Refer to

Figure 103: Transfer sequence diagram for slave receiver on page 293

6. The ADD10 bit is not set after a NACK reception.

7. The BTF bit is not set after a NACK reception, or in case of an ARLO event.

8. Due to timing constraints, when in standard mode if CCR is less than 9 (i.e. with peripheral clock below 2 MHz) with

fMASTER = fCPU and the event interrupt disabled, the following procedure must be followed:

modify the reset sequence in order to insert at least 5 cycles between each operations in the flag clearing sequence. For

example, when fMASTER = fCPU = 1 MHz, use the following sequence to poll the SB bit:

_label_wait: BTJF I2C_SR1,SB,_label_wait

NOP ;

NOP;

NOP ;

NOP

LD I2C_DR, A ; once executed, the SB bit is then cleared.

9. In slave mode, it is recommended to perform the complete clearing sequence (READ SR1 then READ SR3) after ADDR is

set. Refer to Figure 103: Transfer sequence diagram for slave receiver on page 293.

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