STM8S datasheet(301/467 Pages) STMICROELECTRONICS

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RM0016

Inter-integrated circuit (I2C) interface

319

EV9: ADD10= 1, cleared by reading SR1 register followed by writing DR register.

2. EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence.

3. EV6_3 software sequence must be completed before the ACK pulse of the current byte transfer.

21.4.3

Error conditions

The following are the error conditions which may cause communication to fail.

Bus error (BERR)

This error occurs when the I2C interface detects an external stop or a start condition during

an address or data transfer. In this case:

•

The BERR bit is set and an interrupt is generated if the ITERREN bit is set

•

In the case of the slave: data are discarded and the lines are released by hardware:

–

In the case of a misplaced start, the slave considers it is a restart and waits for an

address or a stop condition.

–

In the case of a misplaced stop, the slave reacts in the same way as for a stop

condition and the lines are released by hardware.

•

In the case of the master: the lines are not released and there is no effect in the state of

the current transmission: software can decide if it wants to abort the current

transmission or not.

Acknowledge failure (AF)

This error occurs when the interface detects a non-acknowledge bit. In this case,

•

The AF bit is set and an interrupt is generated if the ITERREN bit is set

•

A transmitter which receives a NACK must reset the communication:

–

If slave: Lines are released by hardware

–

If master: A stop condition or repeated start must be generated by software

Arbitration lost (ARLO)

This error occurs when the I2C interface detects an arbitration lost condition. In this case,

•

The ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is

set).

•

The I2C interface goes automatically back to slave mode (the MSL bit is cleared)

•

When the I²C loses the arbitration, it is not able to acknowledge its slave address in the

same transfer, but it can acknowledge it after a repeated start from the master.

•

Lines are released by hardware

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