STM8S datasheet(295/467 Pages) STMICROELECTRONICS

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DocID14587 Rev 14

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RM0016

Inter-integrated circuit (I2C) interface

319

Slave address transmission

Then the slave address is sent to the SDA line via the internal shift register.

•

In 10-bit addressing mode, sending the header sequence causes the following event:

–

The ADD10 bit is set by hardware and an interrupt is generated if the ITEVTEN bit

is set.

Then the master waits for a read of the SR1 register followed by a write in the DR

sequencing EV9).

The ADDR bit is set by hardware and an interrupt is generated if the ITEVTEN bit is

set. Then the master waits for a read of the SR1 register followed by a read in the SR3

•

In 7-bit addressing mode, one address byte is sent.

As soon as the address byte is sent,

–

The ADDR bit is set by hardware and an interrupt is generated if the ITEVTEN bit

is set.

Then the master waits for a read of the SR1 register followed by a read in the SR3

The master can decide to enter Transmitter or Receiver mode depending on the LSB of

the slave address sent.

•

In 7-bit addressing mode,

–

To enter Transmitter mode, a master sends the slave address with LSB reset.

–

To enter Receiver mode, a master sends the slave address with LSB set.

•

In 10-bit addressing mode,

–

To enter Transmitter mode, a master sends the header (11110xx0) and then the

slave address, (where xx denotes the two most significant bits of the address).

–

To enter Receiver mode, a master sends the header (11110xx0) and then the

slave address. Then it should send a repeated Start condition followed by the

header (11110xx1), (where xx denotes the two most significant bits of the

address).

The TRA bit indicates whether the master is in Receiver or Transmitter mode.

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