STM8S datasheet(190/467 Pages) STMICROELECTRONICS

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16-bit advanced control timer (TIM1)

RM0016

190/467

DocID14587 Rev 14

17.7.2

Control register 2 (TIM1_CR2)

Address offset: 0x01

Reset value: 0x00

654

3210

Reserved

MMS[2:0]

Reserved

COMS

Reserved

CCPC

rrw

Bit 7 Reserved

Bits 6:4 MMS[2:0]: Master mode selection

These bits select the information to be sent in master mode to the ADC or to the other timers for

synchronization (TRGO). The combination is as follows:

000: Reset - The UG bit from the TIM1_EGR register is used as trigger output (TRGO). If the reset is

generated by the trigger input (clock/trigger mode controller configured in reset mode), the signal on

TRGO is delayed compared to the actual reset.

001: Enable - The counter enable signal is used as trigger output (TRGO). It is used to start several

timers or the ADC to control a window in which a slave timer or the ADC is enabled. The counter

enable signal is generated by a logic OR between the CEN control bit and the trigger input when

configured in trigger gated mode. When the counter enable signal is controlled by the trigger input,

there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description

in TIM1_SMCR register).

010: Update - The update event is selected as trigger output (TRGO)

011: Compare pulse (MATCH1) - The trigger output sends a positive pulse when the CC1IF flag is to

be set (even if it was already high), as soon as a capture or a compare match occurs (TRGO).

100: Compare - OC1REF signal is used as trigger output (TRGO)

101: Compare - OC2REF signal is used as trigger output (TRGO)

110: Compare - OC3REF signal is used as trigger output (TRGO)

111: Compare - OC4REF signal is used as trigger output (TRGO)

Bit3 Reserved, must be kept cleared.

Bit 2 COMS: Capture/compare control update selection

0: When capture/compare control bits are preloaded (CCPC = 1), they are updated by setting the

COMG bit.

1: When capture/compare control bits are preloaded (CCPC = 1), they are updated by setting the

COMG bit or when an rising edge occurs on TRGI.

Note: This bit acts only on channels with complementary outputs.

Bit 1 Reserved, forced by hardware to 0

Bit 0 CCPC: Capture/compare preloaded control

0: The CCiE, CCiNE, CCiP, and CCiNP bits in the TIM1_CCERi registers and the OCiM bit in the

TIM1_CCMRi registers are not preloaded

1: CCiE, CCiNE, CCiP, CCiNP and OCiM bits are preloaded, after having been written, they are

updated only when COMG bit is set in the TIM1_EGR register.

Note: This bit acts only on channels with complementary outputs.

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