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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM8S датащи(PDF) 441 Page - STMicroelectronics |
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STM8S датащи(HTML) 441 Page - STMicroelectronics |
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441 / 467 page  DocID14587 Rev 14 441/467 RM0016 Analog/digital converter (ADC) 454 24.10 Schmitt trigger disable registers The ADC_TDRH and ADC_TDRL registers are used to disable the Schmitt triggers available in the AIN analog input pins. Disabling the Schmitt trigger lowers the power consumption in the I/Os. 24.11 ADC registers 24.11.1 ADC data buffer register x high (ADC_DBxRH) (x=0..7 or 0..9 ) Address offset: 0x00 + 2 * channel number Reset value: 0x00 Note: Data buffer registers are not available for ADC2. The data buffer size and base address are device dependent and are specified in the corresponding datasheet. Note that the data buffer registers and the other ADC registers have different base addresses. 7 654 3210 DBH[7:0] r rrr rrrr Bits 7:0 DBH[7:0] Data bits high These bits are set/reset by hardware and are read only. When the ADC is in buffered continuous or scan mode, they contain the high part of the converted data. The data is in right-aligned or left-aligned format depending on the ALIGN bit. Left Data Alignment These bits contain the eight MSB bits of the converted data. Right Data Alignment These bits contain the (eight ADC data width) MSB bits of the converted data. Remaining bits are tied to zero. See Figure 164. |
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