82845GL datasheet(46/193 Pages) INTEL

46 / 193 page

Intel® 82845G/82845GL/82845GV GMCH Datasheet

To prepare for mapping of the configuration cycles on AGP/PCI_B, the initialization software will

go through the following sequence:

1. Scan all devices residing on the PCI Bus #0 using Type 0 configuration accesses.

2. For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it will

configure the secondary bus of the bridge with the appropriate number and scan further down

the hierarchy. This process includes the configuration of the “virtual” PCI-to-PCI bridges

within the GMCH used to map the AGP device’s address spaces in a software specific manner.

Note: Although initial AGP platform implementations will not support hierarchical buses residing below

AGP, this specification still must define this capability to support PCI-66 compatibility. Note also

that future implementations of the AGP devices may support hierarchical PCI or AGP-like buses

coming out of the root AGP device.

3.4

I/O Mapped Registers

The GMCH contains two registers that reside in the processor I/O address space

− the

Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data

(CONFIG_DATA) Register. The Configuration Address Register enables/disables the

configuration space and determines what portion of configuration space is visible through the

Configuration Data window.

3.4.1

CONFIG_ADDRESS—Configuration Address Register

I/O Address:

0CF8h Accessed as a DWord

Default Value:

00000000h

Access:

R/W

Size:

32 bits

CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DWord. A Byte or Word

reference will “pass through” the Configuration Address Register and hub interface onto the

PCI_A bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device

Number, Function Number, and Register Number for which a subsequent configuration access is

intended.

Figure 3-3. Configuration Mechanism Type 1 Configuration Address to PCI Address Mapping

Reg. Index

PCI Address

AD[31:0]

16 15

8 7

CONFIG_ADDRESS

X X

0 1

2 1

11 10

Device Number Function Number

Bus Number

31 30

Reserved

Function Number

Device Number

Bus Number

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