82845GL datasheet(23/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

Signal Description

2.1

Host Interface Signals

Signal Name

Type

Description

ADS#

I/O

AGTL+

Address Strobe: The processor bus owner asserts ADS# to indicate the first of

two cycles of a request phase.

BNR#

I/O

AGTL+

Block Next Request: This signal is used to block the current request bus

owner from issuing a new requests. This signal is used to dynamically control

the processor bus pipeline depth.

BPRI#

AGTL+

Priority Agent Bus Request: The GMCH is the only Priority Agent on the

processor bus. It asserts this signal to obtain the ownership of the address bus.

This signal has priority over symmetric bus requests and will cause the current

symmetric owner to stop issuing new transactions unless the HLOCK# signal

was asserted.

BREQ0#

AGTL+

Bus Request 0#: The GMCH pulls the processor bus’ BREQ0# signal low

during CPURST#. The signal is sampled by the processor on the active-to-

inactive transition of CPURST#. The minimum setup time for this signal is

4HCLKs. The minimum hold time is 2 clocks and the maximum hold time is 20

HCLKs. BREQ0# is terminated high (pulled up) after the hold time requirement

has been satisfied.

CPURST#

AGTL+

CPU Reset: The CPURST# pin is an output from the GMCH. The GMCH

asserts CPURST# while RSTIN# (PCIRST# from Intel® ICH4) is asserted and

for approximately 1 ms after RSTIN# is deasserted. The CPURST# allows the

processors to begin execution in a known state.

DBSY#

I/O

AGTL+

Data Bus Busy: This signal is used by the data bus owner to hold the data bus

for transfers requiring more than one cycle.

DEFER#

AGTL+

Defer: This signal, when asserted, indicates that the GMCH will terminate the

transaction currently being snooped with either a deferred response or with a

retry response.

DINV_[3:0]#

I/O

AGTL+

Dynamic Bus Inversion: These signals are driven along with the HD_[63:0]#

signals. They indicates if the associated signals are inverted or not.

DINV_[3:0]# are asserted such that the number of data bits driven electrically

low (low voltage) within the corresponding 16-bit group never exceeds 8.

DINV_[x]#

Data Bits

DINV_3#

HD_[63:48]#

DINV_2#

HD_[47:32]#

DINV_1#

HD_[31:16]#

DINV_0#

HD_[15:0]#

DRDY#

I/O

AGTL+

Data Ready: DRDY# is asserted for each cycle that data is transferred.

HA_[31:3]#

I/O

AGTL+

Host Address Bus: HA_[31:3]# connect to the processor address bus. During

processor cycles, HA_[31:3]# are inputs. The GMCH drives HA_[31:3]# during

snoop cycles on behalf of the hub interface and AGP/Secondary PCI initiators.

HA_[31:3]# are transferred at 2X rate. Note that the address is inverted on the

processor bus.

HADSTB_[1:0]#

I/O

AGTL+

Host Address Strobe: HADSTB_[1:0]# are the source synchronous strobes

used to transfer HA[31:3]# and HREQ_[4:0]# at the 2X transfer rate.

Strobe

Address Bits

HADSTB_0#

A[16:3]#, REQ[_4:0]#

HADSTB_1#

A[31:17]#

HD_[63:0]#

I/O

AGTL+

Host Data: These signals are connected to the processor data bus. Data on

HD_[63:0]# is transferred at a 4X rate. Note that the data signals may be

inverted on the processor bus.

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