M95M04-DR datasheet(36/46 Pages) STMICROELECTRONICS

36 / 46 page

DC and AC parameters

M95M04-DR

36/46

DS12179 Rev 1

Table 15. AC characteristics

Test conditions specified in Table 9 and Table 10

Symbol

Alt.

Parameter

VCC ≥ 1.8 V

VCC ≥ 2.5 V

Unit

Min.

Max.

Min.

Max.

fSCK Clock frequency

MHz

tSLCH

tCSS1 S active setup time

tSHCH

tCSS2 S not active setup time

tSHSL

tCS

S Deselect time

tCHSH

tCSH S active hold time

tCHSL

-S not active hold time

tCH(1)

1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)

tCLH Clock high time

tCL(1)

tCLL Clock low time

tCLCH(2)

2. Value guaranteed by characterization, not 100% tested in production.

tRC

Clock rise time

µs

tCHCL(2)

tFC

Clock fall time

µs

tDVCH

tDSU Data in setup time

tCHDX

tDH

Data in hold time

tHHCH

Clock low hold time after HOLD not

active

tHLCH

Clock low hold time after HOLD

active

tCLHL

Clock low set-up time before HOLD

active

0-0-

tCLHH

Clock low set-up time before HOLD

not active

0-0-

tSHQZ(2)

tDIS

Output disable time

tCLQV(3)

3. tCLQV must be compatible with tCL (clock low time): if tSU is the Read setup time of the SPI bus master, then

tCL must be equal to or greater than tCLQV + tSU.

Clock low to output valid

tCLQX

tHO

Output hold time

tQLQH(2)

tRO

Output rise time

tQHQL(2)

tFO

Output fall time

tHHQV

tLZ

HOLD high to output valid

tHLQZ(2)

tHZ

HOLD low to output high-Z

tWC

Write time

5(4)

4. Write time for LID instruction is 10 ms.

-5(4)

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